Tegra: Change Tegra20 to Tegra in common code, prep for T30

Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate.
Convert tegra20_ source file and function names to tegra_, also.

Upcoming Tegra30 port will use common code/defines/names where possible.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>

2 files changed, 17 insertions, 148 deletions

diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index ddfa727..ca8fad8 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -25,7 +25,7 @@
 #include <asm/io.h>
 #include <asm/arch/clk_rst.h>
 #include <asm/arch/clock.h>
-#include "tegra_mmc.h"
+#include <asm/arch/tegra_mmc.h>
 
 /* support 4 mmc hosts */
 struct mmc mmc_dev[4];
@@ -39,31 +39,31 @@ struct mmc_host mmc_host[4];
  * @param host		Structure to fill in (base, reg, mmc_id)
  * @param dev_index	Device index (0-3)
  */
-static void tegra20_get_setup(struct mmc_host *host, int dev_index)
+static void tegra_get_setup(struct mmc_host *host, int dev_index)
 {
-	debug("tegra20_get_base_mmc: dev_index = %d\n", dev_index);
+	debug("tegra_get_setup: dev_index = %d\n", dev_index);
 
 	switch (dev_index) {
 	case 1:
-		host->base = TEGRA20_SDMMC3_BASE;
+		host->base = TEGRA_SDMMC3_BASE;
 		host->mmc_id = PERIPH_ID_SDMMC3;
 		break;
 	case 2:
-		host->base = TEGRA20_SDMMC2_BASE;
+		host->base = TEGRA_SDMMC2_BASE;
 		host->mmc_id = PERIPH_ID_SDMMC2;
 		break;
 	case 3:
-		host->base = TEGRA20_SDMMC1_BASE;
+		host->base = TEGRA_SDMMC1_BASE;
 		host->mmc_id = PERIPH_ID_SDMMC1;
 		break;
 	case 0:
 	default:
-		host->base = TEGRA20_SDMMC4_BASE;
+		host->base = TEGRA_SDMMC4_BASE;
 		host->mmc_id = PERIPH_ID_SDMMC4;
 		break;
 	}
 
-	host->reg = (struct tegra20_mmc *)host->base;
+	host->reg = (struct tegra_mmc *)host->base;
 }
 
 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
@@ -345,7 +345,7 @@ static void mmc_change_clock(struct mmc_host *host, uint clock)
 	debug(" mmc_change_clock called\n");
 
 	/*
-	 * Change Tegra20 SDMMCx clock divisor here. Source is 216MHz,
+	 * Change Tegra SDMMCx clock divisor here. Source is 216MHz,
 	 * PLLP_OUT0
 	 */
 	if (clock == 0)
@@ -494,11 +494,11 @@ static int mmc_core_init(struct mmc *mmc)
 	return 0;
 }
 
-int tegra20_mmc_getcd(struct mmc *mmc)
+int tegra_mmc_getcd(struct mmc *mmc)
 {
 	struct mmc_host *host = (struct mmc_host *)mmc->priv;
 
-	debug("tegra20_mmc_getcd called\n");
+	debug("tegra_mmc_getcd called\n");
 
 	if (host->cd_gpio >= 0)
 		return !gpio_get_value(host->cd_gpio);
@@ -506,13 +506,13 @@ int tegra20_mmc_getcd(struct mmc *mmc)
 	return 1;
 }
 
-int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
+int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
 {
 	struct mmc_host *host;
 	char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
 	struct mmc *mmc;
 
-	debug(" tegra20_mmc_init: index %d, bus width %d "
+	debug(" tegra_mmc_init: index %d, bus width %d "
 		"pwr_gpio %d cd_gpio %d\n",
 		dev_index, bus_width, pwr_gpio, cd_gpio);
 
@@ -521,7 +521,7 @@ int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
 	host->clock = 0;
 	host->pwr_gpio = pwr_gpio;
 	host->cd_gpio = cd_gpio;
-	tegra20_get_setup(host, dev_index);
+	tegra_get_setup(host, dev_index);
 
 	clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
 
@@ -539,12 +539,12 @@ int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
 
 	mmc = &mmc_dev[dev_index];
 
-	sprintf(mmc->name, "Tegra20 SD/MMC");
+	sprintf(mmc->name, "Tegra SD/MMC");
 	mmc->priv = host;
 	mmc->send_cmd = mmc_send_cmd;
 	mmc->set_ios = mmc_set_ios;
 	mmc->init = mmc_core_init;
-	mmc->getcd = tegra20_mmc_getcd;
+	mmc->getcd = tegra_mmc_getcd;
 
 	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 	if (bus_width == 8)
@@ -559,7 +559,7 @@ int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
 	 * max freq is highest HS eMMC clock as per the SD/MMC spec
 	 *  (actually 52MHz)
 	 * Both of these are the closest equivalents w/216MHz source
-	 *  clock and Tegra20 SDMMC divisors.
+	 *  clock and Tegra SDMMC divisors.
 	 */
 	mmc->f_min = 375000;
 	mmc->f_max = 48000000;
diff --git a/drivers/mmc/tegra_mmc.h b/drivers/mmc/tegra_mmc.h
deleted file mode 100644
index b1f2564..0000000
--- a/drivers/mmc/tegra_mmc.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * (C) Copyright 2009 SAMSUNG Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Portions Copyright (C) 2011-2012 NVIDIA Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#ifndef __TEGRA_MMC_H_
-#define __TEGRA_MMC_H_
-
-#define TEGRA20_SDMMC1_BASE	0xC8000000
-#define TEGRA20_SDMMC2_BASE	0xC8000200
-#define TEGRA20_SDMMC3_BASE	0xC8000400
-#define TEGRA20_SDMMC4_BASE	0xC8000600
-
-#ifndef __ASSEMBLY__
-struct tegra20_mmc {
-	unsigned int	sysad;		/* _SYSTEM_ADDRESS_0 */
-	unsigned short	blksize;	/* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
-	unsigned short	blkcnt;		/* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
-	unsigned int	argument;	/* _ARGUMENT_0 */
-	unsigned short	trnmod;		/* _CMD_XFER_MODE_0 15:00 xfer mode */
-	unsigned short	cmdreg;		/* _CMD_XFER_MODE_0 31:16 cmd reg */
-	unsigned int	rspreg0;	/* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
-	unsigned int	rspreg1;	/* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
-	unsigned int	rspreg2;	/* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
-	unsigned int	rspreg3;	/* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
-	unsigned int	bdata;		/* _BUFFER_DATA_PORT_0 */
-	unsigned int	prnsts;		/* _PRESENT_STATE_0 */
-	unsigned char	hostctl;	/* _POWER_CONTROL_HOST_0 7:00 */
-	unsigned char	pwrcon;		/* _POWER_CONTROL_HOST_0 15:8 */
-	unsigned char	blkgap;		/* _POWER_CONTROL_HOST_9 23:16 */
-	unsigned char	wakcon;		/* _POWER_CONTROL_HOST_0 31:24 */
-	unsigned short	clkcon;		/* _CLOCK_CONTROL_0 15:00 */
-	unsigned char	timeoutcon;	/* _TIMEOUT_CTRL 23:16 */
-	unsigned char	swrst;		/* _SW_RESET_ 31:24 */
-	unsigned int	norintsts;	/* _INTERRUPT_STATUS_0 */
-	unsigned int	norintstsen;	/* _INTERRUPT_STATUS_ENABLE_0 */
-	unsigned int	norintsigen;	/* _INTERRUPT_SIGNAL_ENABLE_0 */
-	unsigned short	acmd12errsts;	/* _AUTO_CMD12_ERR_STATUS_0 15:00 */
-	unsigned char	res1[2];	/* _RESERVED 31:16 */
-	unsigned int	capareg;	/* _CAPABILITIES_0 */
-	unsigned char	res2[4];	/* RESERVED, offset 44h-47h */
-	unsigned int	maxcurr;	/* _MAXIMUM_CURRENT_0 */
-	unsigned char	res3[4];	/* RESERVED, offset 4Ch-4Fh */
-	unsigned short	setacmd12err;	/* offset 50h */
-	unsigned short	setinterr;	/* offset 52h */
-	unsigned char	admaerr;	/* offset 54h */
-	unsigned char	res4[3];	/* RESERVED, offset 55h-57h */
-	unsigned long	admaaddr;	/* offset 58h-5Fh */
-	unsigned char	res5[0x9c];	/* RESERVED, offset 60h-FBh */
-	unsigned short	slotintstatus;	/* offset FCh */
-	unsigned short	hcver;		/* HOST Version */
-	unsigned char	res6[0x100];	/* RESERVED, offset 100h-1FFh */
-};
-
-#define TEGRA_MMC_HOSTCTL_DMASEL_MASK				(3 << 3)
-#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA				(0 << 3)
-#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT			(2 << 3)
-#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT			(3 << 3)
-
-#define TEGRA_MMC_TRNMOD_DMA_ENABLE				(1 << 0)
-#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE			(1 << 1)
-#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE		(0 << 4)
-#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ			(1 << 4)
-#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT			(1 << 5)
-
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK			(3 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE		(0 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136		(1 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48		(2 << 0)
-#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY	(3 << 0)
-
-#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK				(1 << 3)
-#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK			(1 << 4)
-#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER	(1 << 5)
-
-#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD			(1 << 0)
-#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT			(1 << 1)
-
-#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE			(1 << 0)
-#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE			(1 << 1)
-#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE			(1 << 2)
-
-#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT			8
-#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK			(0xff << 8)
-
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL			(1 << 0)
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE			(1 << 1)
-#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE			(1 << 2)
-
-#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE			(1 << 0)
-#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE			(1 << 1)
-#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT			(1 << 3)
-#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT			(1 << 15)
-#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT				(1 << 16)
-
-#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE			(1 << 0)
-#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE			(1 << 1)
-#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT			(1 << 3)
-#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY		(1 << 4)
-#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY			(1 << 5)
-
-#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE			(1 << 1)
-
-struct mmc_host {
-	struct tegra20_mmc *reg;
-	unsigned int version;	/* SDHCI spec. version */
-	unsigned int clock;	/* Current clock (MHz) */
-	unsigned int base;	/* Base address, SDMMC1/2/3/4 */
-	enum periph_id mmc_id;	/* Peripheral ID: PERIPH_ID_... */
-	int pwr_gpio;		/* Power GPIO */
-	int cd_gpio;		/* Change Detect GPIO */
-};
-
-#endif	/* __ASSEMBLY__ */
-#endif	/* __TEGRA_MMC_H_ */