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authorYangbo Lu <yangbo.lu@freescale.com>2015-04-22 13:57:40 +0800
committerYork Sun <yorksun@freescale.com>2015-05-04 09:25:39 -0700
commit2d9ca2c72c0fce33052f78f02cdc8ad0a5cf4292 (patch)
tree5f175881751b0f63276b58adc59e07cdc5ef3ca8 /drivers/mmc
parentb46cf1b178c7e79240dd8ddb700b3394afbb4192 (diff)
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mmc: fsl_esdhc: Add peripheral clock support
The SD clock could be generated by platform clock or peripheral clock for some platforms. This patch adds peripheral clock support for T1024/T1040/T2080. To enable it, define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/fsl_esdhc.c41
1 files changed, 41 insertions, 0 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 270ec1c..c690a97 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -506,11 +506,47 @@ static void set_sysctl(struct mmc *mmc, uint clock)
esdhc_setbits32(&regs->sysctl, clk);
}
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+static void esdhc_clock_control(struct mmc *mmc, bool enable)
+{
+ struct fsl_esdhc_cfg *cfg = mmc->priv;
+ struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+ u32 value;
+ u32 time_out;
+
+ value = esdhc_read32(&regs->sysctl);
+
+ if (enable)
+ value |= SYSCTL_CKEN;
+ else
+ value &= ~SYSCTL_CKEN;
+
+ esdhc_write32(&regs->sysctl, value);
+
+ time_out = 20;
+ value = PRSSTAT_SDSTB;
+ while (!(esdhc_read32(&regs->prsstat) & value)) {
+ if (time_out == 0) {
+ printf("fsl_esdhc: Internal clock never stabilised.\n");
+ break;
+ }
+ time_out--;
+ mdelay(1);
+ }
+}
+#endif
+
static void esdhc_set_ios(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+ /* Select to use peripheral clock */
+ esdhc_clock_control(mmc, false);
+ esdhc_setbits32(&regs->scr, ESDHCCTL_PCS);
+ esdhc_clock_control(mmc, true);
+#endif
/* Set the clock speed */
set_sysctl(mmc, mmc->clock);
@@ -740,8 +776,13 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd)
}
#endif
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+ do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
+ gd->arch.sdhc_clk, 1);
+#else
do_fixup_by_compat_u32(blob, compat, "clock-frequency",
gd->arch.sdhc_clk, 1);
+#endif
#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
do_fixup_by_compat_u32(blob, compat, "adapter-type",
(u32)(gd->arch.sdhc_adapter), 1);