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| author | Ye Li <ye.li@nxp.com> | 2016-02-19 13:24:09 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2016-03-25 11:17:54 +0800 |
| commit | 199a386428a7ec25d60867ffac7fc5134dc50e6a (patch) | |
| tree | 845a60f54694e355098db0ded4ccf3cdf69f1568 /drivers/mmc | |
| parent | b7724cb4a35890989e822f41a6a854fe5837dd72 (diff) | |
| download | u-boot-imx-199a386428a7ec25d60867ffac7fc5134dc50e6a.zip u-boot-imx-199a386428a7ec25d60867ffac7fc5134dc50e6a.tar.gz u-boot-imx-199a386428a7ec25d60867ffac7fc5134dc50e6a.tar.bz2 | |
MLK-12417 fsl_esdhc: Update clock enable bits for USDHC
The USDHC move the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN,
HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec
register. The community driver uses RSTA to replace the clock gate off
operation. But this is not a good solution. This is because:
1. when using RSTA, we should wait this bit to clear by itself. This is not
implemeneted in the codes.
2. After RSTA is set, it is recommended that the Host Driver reset the
external card and reinitialize it.
So in this patch, we change to use the vendorspec registers for these bits
operation.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index d887d97..b2f0dac 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -518,7 +518,7 @@ static void set_sysctl(struct mmc *mmc, uint clock) clk = (pre_div << 8) | (div << 4); #ifdef CONFIG_FSL_USDHC - esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); + esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); #else esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); #endif @@ -528,7 +528,7 @@ static void set_sysctl(struct mmc *mmc, uint clock) udelay(10000); #ifdef CONFIG_FSL_USDHC - esdhc_clrbits32(®s->sysctl, SYSCTL_RSTA); + esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); #else esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); #endif @@ -623,6 +623,8 @@ static int esdhc_init(struct mmc *mmc) #ifndef CONFIG_FSL_USDHC esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); +#else + esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); #endif /* Set the initial clock speed */ @@ -698,6 +700,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) #ifndef CONFIG_FSL_USDHC esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | SYSCTL_IPGEN | SYSCTL_CKEN); +#else + esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_HCKEN + | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); #endif writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); |