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| author | Anish Trivedi <anish@freescale.com> | 2011-09-13 18:17:31 -0500 |
|---|---|---|
| committer | Anish Trivedi <anish@freescale.com> | 2011-09-13 18:32:07 -0500 |
| commit | a77c6fec8596891be96b2cdbc742c9824844b92a (patch) | |
| tree | 733312d4b1a6a0dfae9466bd8e875c5da798bf11 /drivers/mmc | |
| parent | e436525a70fe47623d346bc7d9f08f12ff8ad787 (diff) | |
| download | u-boot-imx-a77c6fec8596891be96b2cdbc742c9824844b92a.zip u-boot-imx-a77c6fec8596891be96b2cdbc742c9824844b92a.tar.gz u-boot-imx-a77c6fec8596891be96b2cdbc742c9824844b92a.tar.bz2 | |
ENGR00156670-1 ESDHC/USDHC: Remove delay before each cmd and some bug fixes
Removed delay of 10 ms before each command. There should not be
a need to have this delay after the ENGR00156405 patch that polls
until card is not busy anymore before proceeding to next cmd.
Added poll on reset bits of controller after the bits are set to
wait until they clear before proceeding further.
Signed-off-by: Tony Lin <tony.lin@freescale.com>
Signed-off-by: Anish Trivedi <anish@freescale.com>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/imx_esdhc.c | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/drivers/mmc/imx_esdhc.c b/drivers/mmc/imx_esdhc.c index 489fd6a..a326f87 100644 --- a/drivers/mmc/imx_esdhc.c +++ b/drivers/mmc/imx_esdhc.c @@ -185,13 +185,6 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) while (readl(®s->prsstat) & PRSSTAT_DLA); - /* Wait at least 8 SD clock cycles before the next command */ - /* - * Note: This is way more than 8 cycles, but 1ms seems to - * resolve timing issues with some cards - */ - udelay(10000); - /* Set up for a data transfer if we have one */ if (data) { int err; @@ -232,9 +225,18 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) irqstat = readl(®s->irqstat); writel(irqstat, ®s->irqstat); - /* Reset CMD portion on error */ + /* Reset CMD and DATA portions on error */ if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) { writel(readl(®s->sysctl) | SYSCTL_RSTC, ®s->sysctl); + while (readl(®s->sysctl) & SYSCTL_RSTC) + ; + + if (data) { + writel(readl(®s->sysctl) | SYSCTL_RSTD, + ®s->sysctl); + while (readl(®s->sysctl) & SYSCTL_RSTD) + ; + } /* Restore auto-clock gate if error */ if (!cfg->is_usdhc && !data && (cmd->resp_type & MMC_RSP_BUSY)) @@ -327,6 +329,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (readl(®s->irqstat) & 0xFFFF0000) { writel(readl(®s->sysctl) | SYSCTL_RSTC | SYSCTL_RSTD, ®s->sysctl); + while (readl(®s->sysctl) & (SYSCTL_RSTC | SYSCTL_RSTD)) + ; + return COMM_ERR; } writel(-1, ®s->irqstat); |