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authorHaijun.Zhang <Haijun.Zhang@freescale.com>2014-01-10 13:52:18 +0800
committerYork Sun <yorksun@freescale.com>2014-01-22 08:56:34 -0800
commitd47e3d27078dd7419c41e1f8f56dcc221511dd5d (patch)
tree4c20938c8d78343fd3c97af3959800e1cbdc1c59 /drivers/mmc/fsl_esdhc.c
parentf7e27cc5ee13aebce4e81fcf908d22d2d55d61e0 (diff)
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esdhc: Detecting 8 bit width before mmc initialization
The upper 4 data signals of esdhc are shared with spi flash. So detect if the upper 4 pins are assigned to esdhc before enable sdhc 8 bit width. Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/mmc/fsl_esdhc.c')
-rw-r--r--drivers/mmc/fsl_esdhc.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index f79f167..7b146a3 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -596,6 +596,11 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
if (caps & ESDHC_HOSTCAPBLT_HSS)
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
+ if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
+ mmc->host_caps &= ~MMC_MODE_8BIT;
+#endif
+
mmc->f_min = 400000;
mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);