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| author | Dirk Behme <dirk.behme@de.bosch.com> | 2013-07-15 15:44:29 +0200 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-07-16 18:44:23 -0500 |
| commit | a61da72bda80e09f36afbc9037a8c8b63b482de4 (patch) | |
| tree | d9eb4e8aa5bcbf9bbf6455bca097ca4296b0c599 /drivers/mmc/fsl_esdhc.c | |
| parent | ca6d4d0f8f0fb8ae09a7ba271177367bdfdf3136 (diff) | |
| download | u-boot-imx-a61da72bda80e09f36afbc9037a8c8b63b482de4.zip u-boot-imx-a61da72bda80e09f36afbc9037a8c8b63b482de4.tar.gz u-boot-imx-a61da72bda80e09f36afbc9037a8c8b63b482de4.tar.bz2 | |
fsl_esdhc: Touch only relevant sys ctrl bits
Dealing with the sys ctrl register should touch only the
relevant bits and not accidently the whole register. On i.MX6,
the sys control register contains bits which shouldn't be reset to
0, e.g. SYS_CTRL[3-0] and IPP_RST_N (SYS_CTRL[23]).
Do this by read/modify/write instead of just a 32bit write.
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'drivers/mmc/fsl_esdhc.c')
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 4e43e3e..eba1de3 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -470,7 +470,7 @@ static int esdhc_init(struct mmc *mmc) int timeout = 1000; /* Reset the entire host controller */ - esdhc_write32(®s->sysctl, SYSCTL_RSTA); + esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); /* Wait until the controller is available */ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) @@ -481,7 +481,7 @@ static int esdhc_init(struct mmc *mmc) esdhc_write32(®s->scr, 0x00000040); #endif - esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); + esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); /* Set the initial clock speed */ mmc_set_clock(mmc, 400000); @@ -515,7 +515,7 @@ static void esdhc_reset(struct fsl_esdhc *regs) unsigned long timeout = 100; /* wait max 100 ms */ /* reset the controller */ - esdhc_write32(®s->sysctl, SYSCTL_RSTA); + esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); /* hardware clears the bit when it is done */ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) |