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authorAndrew Gabbasov <andrew_gabbasov@mentor.com>2013-04-07 23:06:08 +0000
committerStefano Babic <sbabic@denx.de>2013-04-14 11:22:47 +0200
commit9b74dc56fba2b9db39420f81c990284f36d5801f (patch)
treede12f8c9a57135903b70ae9895fdc8a97397fee7 /drivers/mmc/fsl_esdhc.c
parent54899fc8fe7b33cbe1a7179e39d24e75ababcdc6 (diff)
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fsl_esdhc: Fix DMA transfer completion waiting loop
Rework the waiting for transfer completion loop condition to continue waiting until both Transfer Complete and DMA End interrupts occur. Checking of DLA bit in Present State register looks not needed in addition to interrupts status checking, so it can be removed from the condition. Also, DMA Error condition is added to the list of data errors, checked in the loop. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Diffstat (limited to 'drivers/mmc/fsl_esdhc.c')
-rw-r--r--drivers/mmc/fsl_esdhc.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 737b812..e945c0a 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -397,8 +397,7 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
if (irqstat & DATA_ERR)
return COMM_ERR;
- } while (!(irqstat & IRQSTAT_TC) &&
- (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
+ } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
#endif
if (data->flags & MMC_DATA_READ)
check_and_invalidate_dcache_range(cmd, data);