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| author | wdenk <wdenk> | 2004-06-09 00:10:59 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-06-09 00:10:59 +0000 |
| commit | 356a0d9f3123b57392935febd300ce32e63f1278 (patch) | |
| tree | ac7c15b22c86a9c0c1d927bd300dc90847014cef /drivers/inca-ip_sw.c | |
| parent | 1eaeb58e3c0022812b70d717bf1f458cfb48fdd3 (diff) | |
| download | u-boot-imx-356a0d9f3123b57392935febd300ce32e63f1278.zip u-boot-imx-356a0d9f3123b57392935febd300ce32e63f1278.tar.gz u-boot-imx-356a0d9f3123b57392935febd300ce32e63f1278.tar.bz2 | |
Patch by Markus Pietrek, 04 May 2004:
Fix clear_bss code for ARM systems (all except s3c44b0 which
doesn't clear BSS at all?)
Diffstat (limited to 'drivers/inca-ip_sw.c')
| -rw-r--r-- | drivers/inca-ip_sw.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/inca-ip_sw.c b/drivers/inca-ip_sw.c index f8fe52e..ab22b4d 100644 --- a/drivers/inca-ip_sw.c +++ b/drivers/inca-ip_sw.c @@ -41,13 +41,21 @@ #define DELAY udelay(10000) + /* Sometimes the store word instruction hangs while writing to one + * of the Switch registers. Moving the instruction into a separate + * function somehow makes the problem go away. + */ +static void SWORD(volatile u32 * reg, u32 value) +{ + *reg = value; +} #define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value; #define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg) #define SW_WRITE_REG(reg, value) \ - *((volatile u32*)reg) = (u32)value;\ + SWORD(reg, value);\ DELAY;\ - *((volatile u32*)reg) = (u32)value; + SWORD(reg, value); #define SW_READ_REG(reg, value) \ value = (u32)*((volatile u32*)reg);\ |