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authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>2014-11-04 13:28:50 +0900
committerHeiko Schocher <hs@denx.de>2014-11-10 06:47:37 +0100
commitcd818a381ddcdc2440a167757394298f28b70240 (patch)
tree3cd737afa41f0024748785127c58bf973ce8528a /drivers/i2c/rcar_i2c.c
parent6dd38cc35245db624443ee596eb78853fa9cca7a (diff)
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i2c: rcar_i2c: Fix order of restart and clear status
In case of repeated START condition, the restart has to be kicked before clear status (MSR register). If it is kicked after clear status, R-Car I2C may transfer data (TXD register) or receive data (RXD register) instead of transferring slave address (MAR register). Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Diffstat (limited to 'drivers/i2c/rcar_i2c.c')
-rw-r--r--drivers/i2c/rcar_i2c.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
index 50cebd6..90ad116 100644
--- a/drivers/i2c/rcar_i2c.c
+++ b/drivers/i2c/rcar_i2c.c
@@ -119,10 +119,10 @@ rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr)
/* set slave address, receive */
writel((chip << 1) | 1, &dev->icmar);
- /* clear status */
- writel(0, &dev->icmsr);
/* start master receive */
writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
+ /* clear status */
+ writel(0, &dev->icmsr);
while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDR))
!= (MSR_MAT | MSR_MDR))