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authorYork Sun <yorksun@freescale.com>2014-06-23 15:15:54 -0700
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-07-03 08:40:51 +0200
commit2f78eae5064728d6cd907148cfeaf8ba3e63b0ef (patch)
tree80b5d23e3c6d46424909954cbc9504288e8f7156 /drivers/i2c/mxc_i2c.c
parent22932ffc03e521130cfd33cae1fc2531eb42604a (diff)
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ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Diffstat (limited to 'drivers/i2c/mxc_i2c.c')
-rw-r--r--drivers/i2c/mxc_i2c.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 48468d7..c14797c 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -429,6 +429,11 @@ static void * const i2c_bases[] = {
(void *)I2C3_BASE_ADDR
#elif defined(CONFIG_VF610)
(void *)I2C0_BASE_ADDR
+#elif defined(CONFIG_FSL_LSCH3)
+ (void *)I2C1_BASE_ADDR,
+ (void *)I2C2_BASE_ADDR,
+ (void *)I2C3_BASE_ADDR,
+ (void *)I2C4_BASE_ADDR
#else
#error "architecture not supported"
#endif