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authorLinus Walleij <linus.walleij@linaro.org>2012-03-03 21:21:13 +0100
committerWolfgang Denk <wd@denx.de>2012-03-04 21:15:31 +0100
commitfca94c3fd5deef33442813475a5af1650f2d2830 (patch)
tree0425cb4f148171801e6f1dcbd0d93da3aa43196d /drivers/fpga
parenta1e47b66d98f5caf19895965cfe38c176bbf01e8 (diff)
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integrator: remove fragile delay loop from PCI code
The reference implementation of the PCI initialization code almost everywhere contain this fragile loop of "a few usecs", and its use of volatile variables to delay a number of bus cycles is indeed uncertain. Reading the manual "Integrator/AP Users Guide", page 5-15 it is clearly stated: "Wait until 230ms after the end of the reset period before accessing V360EPC internal registers. The V360EPC supports the use of a serial configuration PROM and the software must wait for the device to detect the absence of this PROM before accessing any registers. The required delay is a function of the PCI Clock, but at the lower frequency (25MHz) is 230ms". So let's simply wait 230ms per the spec. This solves the compilation error that looked like this: pci.c: In function ‘pci_init_board’: pci.c:286:18: warning: variable ‘j’ set but not used Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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