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| author | Michal Simek <michal.simek@xilinx.com> | 2014-05-02 14:15:27 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2014-05-20 15:23:46 +0200 |
| commit | 5b815c9c61499a3a0a4b9a16ac9d08cf83d31fd3 (patch) | |
| tree | eee49d50841f2ca8c57004cfb6379d283fd7cd6c /drivers/fpga | |
| parent | 67193864bce78b38fda2c73b9918403d1c572fcc (diff) | |
| download | u-boot-imx-5b815c9c61499a3a0a4b9a16ac9d08cf83d31fd3.zip u-boot-imx-5b815c9c61499a3a0a4b9a16ac9d08cf83d31fd3.tar.gz u-boot-imx-5b815c9c61499a3a0a4b9a16ac9d08cf83d31fd3.tar.bz2 | |
fpga: zynqpl: Clean partial bitstream handling
Do not do partial bitstream detection based on bitstream
size and use bitstream_type argument which is passed
from the fpga core.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/fpga')
| -rw-r--r-- | drivers/fpga/zynqpl.c | 18 |
1 files changed, 6 insertions, 12 deletions
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 572c078..915f077 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -194,7 +194,7 @@ static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen) return FPGA_SUCCESS; } -static int zynq_dma_xfer_init(u32 partialbit) +static int zynq_dma_xfer_init(bitstream_type bstype) { u32 status, control, isr_status; unsigned long ts; @@ -202,7 +202,7 @@ static int zynq_dma_xfer_init(u32 partialbit) /* Clear loopback bit */ clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); - if (!partialbit) { + if (bstype != BIT_PARTIAL) { zynq_slcr_devcfg_disable(); /* Setting PCFG_PROG_B signal to high */ @@ -322,16 +322,11 @@ static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap) static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf, size_t bsize, u32 blocksize, u32 *swap, - u32 *partialbit) + bitstream_type *bstype) { u32 *buf_start; u32 diff; - /* Detect if we are going working with partial or full bitstream */ - if (bsize != desc->size) { - printf("%s: Working with partial bitstream\n", __func__); - *partialbit = 1; - } buf_start = check_data((u8 *)buf, blocksize, swap); if (!buf_start) @@ -351,7 +346,7 @@ static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf, return FPGA_FAIL; } - if (zynq_dma_xfer_init(*partialbit)) + if (zynq_dma_xfer_init(*bstype)) return FPGA_FAIL; return 0; @@ -361,7 +356,6 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize, bitstream_type bstype) { unsigned long ts; /* Timestamp */ - u32 partialbit = 0; u32 isr_status, swap; /* @@ -369,7 +363,7 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize, * in chunks */ if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap, - &partialbit)) + &bstype)) return FPGA_FAIL; buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap); @@ -398,7 +392,7 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize, debug("%s: FPGA config done\n", __func__); - if (!partialbit) + if (bstype != BIT_PARTIAL) zynq_slcr_devcfg_enable(); return FPGA_SUCCESS; |