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| author | Anish Trivedi <anish@freescale.com> | 2011-09-09 14:01:24 -0500 |
|---|---|---|
| committer | Anish Trivedi <anish@freescale.com> | 2011-09-13 10:12:25 -0500 |
| commit | e436525a70fe47623d346bc7d9f08f12ff8ad787 (patch) | |
| tree | a267ee5afbf84e7b708af1749b0116e34c642f74 /drivers/fpga | |
| parent | ecee97c3abeaf39c1d862c47cc6f0e9a55865ed0 (diff) | |
| download | u-boot-imx-e436525a70fe47623d346bc7d9f08f12ff8ad787.zip u-boot-imx-e436525a70fe47623d346bc7d9f08f12ff8ad787.tar.gz u-boot-imx-e436525a70fe47623d346bc7d9f08f12ff8ad787.tar.bz2 | |
ENGR00156405 ESDHC: Add workaround for auto-clock gate errata ENGcm03648
The errata, not applicable to USDHC, causes ESDHC to shut off clock to
the card when auto-clock gating is enabled for commands with busy
signalling and no data phase. The card might require the clock to exit
the busy state, so the workaround is to disable the auto-clock gate
bits in SYSCTL register for such commands. The workaround also entails
polling on DAT0 bit in the PRSSTAT register to learn when busy state is
complete. Auto-clock gating is re-enabled at the end of busy state.
Signed-off-by: Anish Trivedi <anish@freescale.com>
Diffstat (limited to 'drivers/fpga')
0 files changed, 0 insertions, 0 deletions