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| author | Marek Vasut <marex@denx.de> | 2015-08-02 19:21:56 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-08-08 14:14:29 +0200 |
| commit | 98cfc9058bf4b4019bac34765d235d2dcb0192bb (patch) | |
| tree | 827d881445d2904abb996b6b015233c366469722 /drivers/ddr | |
| parent | 042ff2d0facaa520f1bc02b0695eb6a4e1d30b7a (diff) | |
| download | u-boot-imx-98cfc9058bf4b4019bac34765d235d2dcb0192bb.zip u-boot-imx-98cfc9058bf4b4019bac34765d235d2dcb0192bb.tar.gz u-boot-imx-98cfc9058bf4b4019bac34765d235d2dcb0192bb.tar.bz2 | |
ddr: altera: sequencer: Zap VFIFO_SIZE
Just use READ_VALID_FIFO_SIZE directly, no need for this macro obfuscation.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/altera/sequencer.c | 8 | ||||
| -rw-r--r-- | drivers/ddr/altera/sequencer.h | 3 |
2 files changed, 4 insertions, 7 deletions
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 70956fa..dd72566 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -1507,7 +1507,7 @@ static void rw_mgr_decr_vfifo(const u32 grp) { u32 i; - for (i = 0; i < VFIFO_SIZE - 1; i++) + for (i = 0; i < READ_VALID_FIFO_SIZE - 1; i++) rw_mgr_incr_vfifo(grp); } @@ -1521,7 +1521,7 @@ static int find_vfifo_failing_read(const u32 grp) { u32 v, ret, fail_cnt = 0; - for (v = 0; v < VFIFO_SIZE; v++) { + for (v = 0; v < READ_VALID_FIFO_SIZE; v++) { debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n", __func__, __LINE__, v); ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, @@ -1592,7 +1592,7 @@ static int sdr_find_phase_delay(int working, int delay, const u32 grp, static int sdr_find_phase(int working, const u32 grp, u32 *work, u32 *i, u32 *p) { - const u32 end = VFIFO_SIZE + (working ? 0 : 1); + const u32 end = READ_VALID_FIFO_SIZE + (working ? 0 : 1); int ret; for (; *i < end; (*i)++) { @@ -1773,7 +1773,7 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn, * push vfifo until we can successfully calibrate. We can do this * because the largest possible margin in 1 VFIFO cycle. */ - for (i = 0; i < VFIFO_SIZE; i++) { + for (i = 0; i < READ_VALID_FIFO_SIZE; i++) { debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n"); if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1, PASS_ONE_BIT, diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h index 3f6f7b6..a80f227 100644 --- a/drivers/ddr/altera/sequencer.h +++ b/drivers/ddr/altera/sequencer.h @@ -65,9 +65,6 @@ #define CAL_SUBSTAGE_READ_LATENCY 1 #define CAL_SUBSTAGE_REFRESH 1 -/* length of VFIFO, from SW_MACROS */ -#define VFIFO_SIZE (READ_VALID_FIFO_SIZE) - #define SCC_MGR_GROUP_COUNTER_OFFSET 0x0000 #define SCC_MGR_DQS_IN_DELAY_OFFSET 0x0100 #define SCC_MGR_DQS_EN_PHASE_OFFSET 0x0200 |