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| author | Marek Vasut <marex@denx.de> | 2015-07-17 05:30:14 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-08-08 14:14:13 +0200 |
| commit | 8eccde3ebbda8738862cbffb07d8f5f8165b44ab (patch) | |
| tree | 2bba69fbdd6dd2105d6106f3a43c9b68425eea16 /drivers/ddr | |
| parent | d41ea93a33416b23dc6102c2afc4cf53a80b773f (diff) | |
| download | u-boot-imx-8eccde3ebbda8738862cbffb07d8f5f8165b44ab.zip u-boot-imx-8eccde3ebbda8738862cbffb07d8f5f8165b44ab.tar.gz u-boot-imx-8eccde3ebbda8738862cbffb07d8f5f8165b44ab.tar.bz2 | |
ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add() cleanup part 1
Apparently, in case of the DQ and DM, the value if the new_delay variable
is calculated, but the value is not used. Zap the entire code which does
calculate the value.
It is not clear to me whether or not the code is doing the right thing
in the first place. Right now, it calls scc_mgr_load_dq() and
scc_mgr_load_dm() respectively, but I suspect it might need to call
scc_mgr_apply_group_dq_out1_delay() and scc_mgr_apply_group_dm_out1_delay()
instead. This is something Altera must investigate.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/altera/sequencer.c | 44 |
1 files changed, 9 insertions, 35 deletions
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 3a95a53..11213c6 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -664,45 +664,19 @@ static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group, } /* apply a delay to the entire output side: DQ, DM, DQS, OCT */ -static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group, - uint32_t group_bgn, - uint32_t delay) -{ - uint32_t i, p, new_delay; - - /* dq shift */ - for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) { - new_delay = READ_SCC_DQ_OUT2_DELAY; - new_delay += delay; - - if (new_delay > IO_IO_OUT2_DELAY_MAX) { - debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQ[%u,%u]:\ - %u > %lu => %lu", __func__, __LINE__, - write_group, group_bgn, delay, i, p, new_delay, - (long unsigned int)IO_IO_OUT2_DELAY_MAX, - (long unsigned int)IO_IO_OUT2_DELAY_MAX); - new_delay = IO_IO_OUT2_DELAY_MAX; - } +static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group, + const u32 group_bgn, + const u32 delay) +{ + u32 i, new_delay; + /* DQ shift */ + for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) scc_mgr_load_dq(i); - } - - /* dm shift */ - for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { - new_delay = READ_SCC_DM_IO_OUT2_DELAY; - new_delay += delay; - - if (new_delay > IO_IO_OUT2_DELAY_MAX) { - debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DM[%u]:\ - %u > %lu => %lu\n", __func__, __LINE__, - write_group, group_bgn, delay, i, new_delay, - (long unsigned int)IO_IO_OUT2_DELAY_MAX, - (long unsigned int)IO_IO_OUT2_DELAY_MAX); - new_delay = IO_IO_OUT2_DELAY_MAX; - } + /* DM shift */ + for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) scc_mgr_load_dm(i); - } /* dqs shift */ new_delay = READ_SCC_DQS_IO_OUT2_DELAY; |