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authorStefan Roese <sr@denx.de>2015-12-10 15:02:38 +0100
committerStefan Roese <sr@denx.de>2016-01-14 14:08:59 +0100
commit698ffab239609e75b8de8f7009c06311e8b0b21a (patch)
treee0f126720e8bcae796da79efdc45c2014a6989ed /drivers/ddr
parentbf0db8b82a0f2e1abcb073fe0b72e6b4ba7c5fe0 (diff)
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arm: mvebu: Make ECC support configurable on Armada XP
Currently, ECC support is enabled for all Armada XP boards. So the DDR3 driver tries to configure the controller with ECC support, even on boards without ECC. This patch makes this ECC optional which now can be configured on a board-per-board basis. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Phil Sutter <phil@nwl.cc>
Diffstat (limited to 'drivers/ddr')
-rw-r--r--drivers/ddr/marvell/axp/ddr3_axp.h3
-rw-r--r--drivers/ddr/marvell/axp/ddr3_axp_config.h5
2 files changed, 8 insertions, 0 deletions
diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h
index d9e33f7..75d315a 100644
--- a/drivers/ddr/marvell/axp/ddr3_axp.h
+++ b/drivers/ddr/marvell/axp/ddr3_axp.h
@@ -33,7 +33,10 @@
#define SAR1_CPU_CORE_MASK 0x00000018
#define SAR1_CPU_CORE_OFFSET 3
+/* Only enable ECC if the board selects it */
+#ifdef CONFIG_BOARD_ECC_SUPPORT
#define ECC_SUPPORT
+#endif
#define NEW_FABRIC_TWSI_ADDR 0x4E
#ifdef CONFIG_DB_784MP_GP
#define BUS_WIDTH_ECC_TWSI_ADDR 0x4E
diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h
index a672044..25c34fb 100644
--- a/drivers/ddr/marvell/axp/ddr3_axp_config.h
+++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h
@@ -44,7 +44,12 @@
* DDR3_TRAINING_DEBUG - Debug prints of internal code
*/
#define DDR_TARGET_FABRIC 5
+/* Only enable ECC if the board selects it */
+#ifdef CONFIG_BOARD_ECC_SUPPORT
#define DRAM_ECC 1
+#else
+#define DRAM_ECC 0
+#endif
#ifdef MV_DDR_32BIT
#define BUS_WIDTH 32