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authorYork Sun <yorksun@freescale.com>2014-06-26 11:14:44 -0700
committerYork Sun <yorksun@freescale.com>2014-07-22 16:25:55 -0700
commit3d75ec95f57224995210db5c5dea8d458cf862fb (patch)
tree4ad21c2e982302743b1d220ae669eef3a26fbb18 /drivers/ddr
parentde5191631088e71ba8ed28bb491dafa776058008 (diff)
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driver/ddr: Fix DDR register timing_cfg_8
The field wrtord_bg should add 2 clocks if on the fly chop is enabled, according to DDR controller manual for DDR4. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr')
-rw-r--r--drivers/ddr/fsl/ctrl_regs.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index dcf6287..04e4178 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1857,6 +1857,9 @@ static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
wrtord_bg = max(4, picos_to_mclk(7500));
+ if (popts->otf_burst_chop_en)
+ wrtord_bg += 2;
+
pre_all_rec = 0;
ddr->timing_cfg_8 = (0