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| author | Dirk Eibach <dirk.eibach@gdsys.cc> | 2015-10-28 16:44:14 +0100 |
|---|---|---|
| committer | Luka Perkov <luka.perkov@sartura.hr> | 2015-11-17 23:41:41 +0100 |
| commit | a21b4f0f9977915f9a609fe8cc8fba2d1a3ba629 (patch) | |
| tree | b945aabb5a613b6985664e6c31e47a1c6b0ceeb1 /drivers/ddr | |
| parent | ea8b6877a84c6e219bc3c7fe3ef08f7124cf4305 (diff) | |
| download | u-boot-imx-a21b4f0f9977915f9a609fe8cc8fba2d1a3ba629.zip u-boot-imx-a21b4f0f9977915f9a609fe8cc8fba2d1a3ba629.tar.gz u-boot-imx-a21b4f0f9977915f9a609fe8cc8fba2d1a3ba629.tar.bz2 | |
arm: mvebu: Fix SAR1_CPU_CORE_MASK
SAR1_CPU_CORE_MASK was wrong, probably copy/paste
from another architecture.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h b/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h index 7500a72..06d0ab1 100644 --- a/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h +++ b/drivers/ddr/marvell/a38x/ddr3_hws_hw_training_def.h @@ -23,8 +23,8 @@ #define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100)) #define CPU_MRVL_ID_OFFSET 0x10 -#define SAR1_CPU_CORE_MASK 0x00000018 -#define SAR1_CPU_CORE_OFFSET 3 +#define SAR1_CPU_CORE_MASK 0x38000000 +#define SAR1_CPU_CORE_OFFSET 27 #define NEW_FABRIC_TWSI_ADDR 0x4e #ifdef DB_784MP_GP @@ -461,7 +461,4 @@ #define CLK_CPU_2200 13 #define CLK_CPU_2400 14 -#define SAR1_CPU_CORE_MASK 0x00000018 -#define SAR1_CPU_CORE_OFFSET 3 - #endif /* _DDR3_HWS_HW_TRAINING_DEF_H */ |