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| author | Dirk Eibach <dirk.eibach@gdsys.cc> | 2015-10-28 16:44:15 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2016-03-24 09:36:40 +0100 |
| commit | 44876bf9e8fc244e5f8a3fc643d07cb0ad3b3775 (patch) | |
| tree | d5ca79ac537bfa03b3bfa28253af0762579354b7 /drivers/ddr | |
| parent | 371b9e9c394d7d96935afbc6fae318fde2fa2760 (diff) | |
| download | u-boot-imx-44876bf9e8fc244e5f8a3fc643d07cb0ad3b3775.zip u-boot-imx-44876bf9e8fc244e5f8a3fc643d07cb0ad3b3775.tar.gz u-boot-imx-44876bf9e8fc244e5f8a3fc643d07cb0ad3b3775.tar.bz2 | |
arm: mvebu: Fix ddr3_init() cpu config
Armada 38x has a maximum of two cores. Probably copy/paste
bug from Armada XP.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_init.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c index 556f877..ee05f57 100644 --- a/drivers/ddr/marvell/a38x/ddr3_init.c +++ b/drivers/ddr/marvell/a38x/ddr3_init.c @@ -305,8 +305,6 @@ int ddr3_init(void) SAR1_CPU_CORE_OFFSET; switch (soc_num) { case 0x3: - reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET); - reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET); case 0x1: reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET); case 0x0: |