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authorYork Sun <yorksun@freescale.com>2014-09-05 13:52:42 +0800
committerYork Sun <yorksun@freescale.com>2014-09-08 10:30:34 -0700
commit5cb27c5d44ac789f0f0583b57c15dc708ca55c69 (patch)
tree588846b83cc53338a24e6ec1e23217ecbc4ef331 /drivers/ddr
parentd28cb6714216cc9e6bfdc1fa333d5dcd174207bd (diff)
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driver/ddr/freescale: Fix DDR3 driver for ARM
Reading DDR register should use ddr_in32() for proper endianess. This patch fixes incorrect waiting time for ARM platforms. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr')
-rw-r--r--drivers/ddr/fsl/arm_ddr_gen3.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index d4ed9ae..59f2fd6 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -194,7 +194,7 @@ step2:
* For example, 2GB on 666MT/s 64-bit bus takes about 402ms
* Let's wait for 800ms
*/
- bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+ bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT);
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
(get_ddr_freq(0) >> 20)) << 1;