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authorYork Sun <yorksun@freescale.com>2014-05-23 13:15:00 -0700
committerYork Sun <yorksun@freescale.com>2014-06-05 13:45:07 -0700
commit9855b3beca648dabe4d86b06d36bf219ebd0732d (patch)
treec0a02085628640beec9e0d69f31af84f00eabb8e /drivers/ddr/fsl
parentaaee5230f135bbfbe7abe6388cd04931f322db68 (diff)
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powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of 0°C and then operated above a junction temperature of 65°C, the DDR controller may cause receive data errors, resulting ECC errors and/or corrupted data. This erratum applies to the following SoCs and their variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023, P2020. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr/fsl')
-rw-r--r--drivers/ddr/fsl/ctrl_regs.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 78e82bb..dcf6287 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -2304,5 +2304,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
ddr->debug[2] = 0x00000400;
ddr->debug[4] = 0xff800000;
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
+ if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
+ ddr->debug[2] |= 0x00000200; /* set bit 22 */
+#endif
+
return check_fsl_memctl_config_regs(ddr);
}