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authorYork Sun <yorksun@freescale.com>2015-01-06 13:18:50 -0800
committerYork Sun <yorksun@freescale.com>2015-02-24 13:09:18 -0800
commit03e664d8f4065010ccb6c75648192200a832fd8b (patch)
treef0398fdcdc87e12da79a82cde310b1a11937641a /drivers/ddr/fsl/util.c
parentb87e6f88e9218da3de371bb6cc8a34924153178e (diff)
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driver/ddr/fsl: Add support for multiple DDR clocks
Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr/fsl/util.c')
-rw-r--r--drivers/ddr/fsl/util.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index 58b519b..ad569de 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -43,9 +43,9 @@ u32 fsl_ddr_get_version(void)
* propagation, compute a suitably rounded mclk_ps to compute
* a working memory controller configuration.
*/
-unsigned int get_memory_clk_period_ps(void)
+unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num)
{
- unsigned int data_rate = get_ddr_freq(0);
+ unsigned int data_rate = get_ddr_freq(ctrl_num);
unsigned int result;
/* Round to nearest 10ps, being careful about 64-bit multiply/divide */
@@ -59,10 +59,10 @@ unsigned int get_memory_clk_period_ps(void)
}
/* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
-unsigned int picos_to_mclk(unsigned int picos)
+unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos)
{
unsigned long long clks, clks_rem;
- unsigned long data_rate = get_ddr_freq(0);
+ unsigned long data_rate = get_ddr_freq(ctrl_num);
/* Short circuit for zero picos */
if (!picos)
@@ -88,9 +88,9 @@ unsigned int picos_to_mclk(unsigned int picos)
return (unsigned int) clks;
}
-unsigned int mclk_to_picos(unsigned int mclk)
+unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk)
{
- return get_memory_clk_period_ps() * mclk;
+ return get_memory_clk_period_ps(ctrl_num) * mclk;
}
#ifdef CONFIG_PPC