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authorYork Sun <yorksun@freescale.com>2015-01-06 13:18:50 -0800
committerYork Sun <yorksun@freescale.com>2015-02-24 13:09:18 -0800
commit03e664d8f4065010ccb6c75648192200a832fd8b (patch)
treef0398fdcdc87e12da79a82cde310b1a11937641a /drivers/ddr/fsl/main.c
parentb87e6f88e9218da3de371bb6cc8a34924153178e (diff)
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driver/ddr/fsl: Add support for multiple DDR clocks
Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr/fsl/main.c')
-rw-r--r--drivers/ddr/fsl/main.c25
1 files changed, 14 insertions, 11 deletions
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 6f291eb..f49939b 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -450,7 +450,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
&(pinfo->spd_installed_dimms[i][j]);
dimm_params_t *pdimm =
&(pinfo->dimm_params[i][j]);
- retval = compute_dimm_parameters(spd, pdimm, i);
+ retval = compute_dimm_parameters(
+ i, spd, pdimm, j);
#ifdef CONFIG_SYS_DDR_RAW_TIMING
if (!i && !j && retval) {
printf("SPD error on controller %d! "
@@ -507,10 +508,11 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
for (i = first_ctrl; i <= last_ctrl; i++) {
debug("Computing lowest common DIMM"
" parameters for memctl=%u\n", i);
- compute_lowest_common_dimm_parameters(
- pinfo->dimm_params[i],
- &timing_params[i],
- CONFIG_DIMM_SLOTS_PER_CTLR);
+ compute_lowest_common_dimm_parameters
+ (i,
+ pinfo->dimm_params[i],
+ &timing_params[i],
+ CONFIG_DIMM_SLOTS_PER_CTLR);
}
case STEP_GATHER_OPTS:
@@ -562,12 +564,13 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
continue;
}
- compute_fsl_memctl_config_regs(
- &pinfo->memctl_opts[i],
- &ddr_reg[i], &timing_params[i],
- pinfo->dimm_params[i],
- dbw_capacity_adjust[i],
- size_only);
+ compute_fsl_memctl_config_regs
+ (i,
+ &pinfo->memctl_opts[i],
+ &ddr_reg[i], &timing_params[i],
+ pinfo->dimm_params[i],
+ dbw_capacity_adjust[i],
+ size_only);
}
default: