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| author | Marek Vasut <marex@denx.de> | 2016-04-04 21:16:18 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2016-04-20 11:28:45 +0200 |
| commit | 70ed80af46e58a25d472362fe5552e1e49eaf25b (patch) | |
| tree | a6eec9f88741935b64ae39157a42f17aab48878e /drivers/ddr/altera | |
| parent | f3f777cdf00433866b1178e23a9a99e2eaf7d89e (diff) | |
| download | u-boot-imx-70ed80af46e58a25d472362fe5552e1e49eaf25b.zip u-boot-imx-70ed80af46e58a25d472362fe5552e1e49eaf25b.tar.gz u-boot-imx-70ed80af46e58a25d472362fe5552e1e49eaf25b.tar.bz2 | |
ddr: altera: Zero DM IN delay in scc_mgr_zero_group()
This one last set of delay configuration registers was not properly
zeroed out originally, fix it and zero them out.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Diffstat (limited to 'drivers/ddr/altera')
| -rw-r--r-- | drivers/ddr/altera/sequencer.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 254b130..0321e3b 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -303,15 +303,22 @@ static void scc_mgr_set_dqs_en_delay(u32 read_group, u32 delay) scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay); } +static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay) +{ + scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay); +} + static void scc_mgr_set_dqs_io_in_delay(u32 delay) { scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs, delay); } -static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay) +static void scc_mgr_set_dm_in_delay(u32 dm, u32 delay) { - scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay); + scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, + rwcfg->mem_dq_per_write_dqs + 1 + dm, + delay); } static void scc_mgr_set_dq_out1_delay(u32 dq_in_group, u32 delay) @@ -584,8 +591,11 @@ static void scc_mgr_zero_group(const u32 write_group, const int out_only) writel(0xff, &sdr_scc_mgr->dq_ena); /* Zero all DM config settings. */ - for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) + for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) { + if (!out_only) + scc_mgr_set_dm_in_delay(i, 0); scc_mgr_set_dm_out1_delay(i, 0); + } /* Multicast to all DM enables. */ writel(0xff, &sdr_scc_mgr->dm_ena); |