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| author | Marek Vasut <marex@denx.de> | 2015-08-02 19:24:12 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-08-08 14:14:29 +0200 |
| commit | 3cd0906cc21bc88bfe318b32a08c5fd8d8915b7f (patch) | |
| tree | 3e2a42cc8f004bfa5c97c81f1d87ed3ead4ef88a /drivers/ddr/altera/sequencer.h | |
| parent | 98cfc9058bf4b4019bac34765d235d2dcb0192bb (diff) | |
| download | u-boot-imx-3cd0906cc21bc88bfe318b32a08c5fd8d8915b7f.zip u-boot-imx-3cd0906cc21bc88bfe318b32a08c5fd8d8915b7f.tar.gz u-boot-imx-3cd0906cc21bc88bfe318b32a08c5fd8d8915b7f.tar.bz2 | |
ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL
This is another macro used to obfuscate the real code. The
T(INIT|RESET)_CNTR._VAL is always defined, so this indirection
is unnecessary. Get rid of this.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'drivers/ddr/altera/sequencer.h')
| -rw-r--r-- | drivers/ddr/altera/sequencer.h | 45 |
1 files changed, 0 insertions, 45 deletions
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h index a80f227..839a374 100644 --- a/drivers/ddr/altera/sequencer.h +++ b/drivers/ddr/altera/sequencer.h @@ -122,51 +122,6 @@ #define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010 #define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020 -/* Init and Reset delay constants - Only use if defined by sequencer_defines.h, - * otherwise, revert to defaults - * Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 = - * 200.75us @ 266MHz - */ -#ifdef TINIT_CNTR0_VAL -#define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL -#else -#define SEQ_TINIT_CNTR0_VAL 0 -#endif - -#ifdef TINIT_CNTR1_VAL -#define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL -#else -#define SEQ_TINIT_CNTR1_VAL 202 -#endif - -#ifdef TINIT_CNTR2_VAL -#define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL -#else -#define SEQ_TINIT_CNTR2_VAL 131 -#endif - - -/* Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 = - * 500.86us @ 266MHz - */ -#ifdef TRESET_CNTR0_VAL -#define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL -#else -#define SEQ_TRESET_CNTR0_VAL 2 -#endif - -#ifdef TRESET_CNTR1_VAL -#define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL -#else -#define SEQ_TRESET_CNTR1_VAL 252 -#endif - -#ifdef TRESET_CNTR2_VAL -#define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL -#else -#define SEQ_TRESET_CNTR2_VAL 131 -#endif - struct socfpga_sdr_rw_load_manager { u32 load_cntr0; u32 load_cntr1; |