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authorAneesh Bansal <aneesh.bansal@freescale.com>2015-12-08 13:54:30 +0530
committerYork Sun <yorksun@freescale.com>2015-12-15 08:57:35 +0800
commit3a4800a5968f689788d70f7decb000a3d3e1a2f4 (patch)
tree45e595cb658089cc2776fa3c7e99be7e04031086 /drivers/crypto
parent9711f52806655bcfa28fe5594b91fed430beb72e (diff)
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drivers/crypto/fsl: fix endianness issue in RNG
For Setting and clearing the bits in SEC Block registers sec_clrbits32() and sec_setbits32() are used which work as per endianness of CAAM block. So these must be used with SEC register address as argument. If the value is read in a local variable, then the functions will not behave correctly where endianness of CAAM and core is different. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> CC: Alex Porosanu <alexandru.porosanu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/crypto')
-rw-r--r--drivers/crypto/fsl/jr.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index f63eacb..b553e3c 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -470,17 +470,13 @@ static void kick_trng(int ent_delay)
sec_out32(&rng->rtfreqmin, ent_delay >> 2);
/* disable maximum frequency count */
sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
- /* read the control register */
- val = sec_in32(&rng->rtmctl);
/*
* select raw sampling in both entropy shifter
* and statistical checker
*/
- sec_setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC);
+ sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
/* put RNG4 into run mode */
- sec_clrbits32(&val, RTMCTL_PRGM);
- /* write back the control register */
- sec_out32(&rng->rtmctl, val);
+ sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
}
static int rng_init(void)