diff options
| author | zhang sanshan <sanshan.zhang@nxp.com> | 2017-05-22 15:17:44 +0800 |
|---|---|---|
| committer | Chen Guoyin <guoyin.chen@nxp.com> | 2017-07-10 15:08:58 +0800 |
| commit | 2c1196079eaf31bd8a7bf5a15e1cbf3c6c7902bb (patch) | |
| tree | 5148602bd0fc6f1d90666fd1d1494bbbc41dbccc /drivers/crypto | |
| parent | ff92794f05268eac978e9ab3e7d97a651819fe36 (diff) | |
| download | u-boot-imx-2c1196079eaf31bd8a7bf5a15e1cbf3c6c7902bb.zip u-boot-imx-2c1196079eaf31bd8a7bf5a15e1cbf3c6c7902bb.tar.gz u-boot-imx-2c1196079eaf31bd8a7bf5a15e1cbf3c6c7902bb.tar.bz2 | |
MA-9409-3 Add base board support for android and android things.
* add board support for android and android things.
mx6ul_nxpu_iopb, pico-6ul, pico-imx7d, aquila-6ul
reorganize the Kconfig, and fix the redefine issue.
* add android configure into configure-while
* add a common file mx_android_common.h
it will be included by android and android things.
defconfig only include ANDROID_THINGS_SUPPORT or ANDROID_SUPPORT
* move partition_table_valid into f_fastboot.c.
it's a common code.
* add invalidate_dcache_range in fixed order.
It will have salt invalid issue if we do not add it in order
* add display for pico-7d.
Change-Id: I6f8a4876c2f8bbd098034d1e3f53033109300bca
Signed-off-by: zhang sanshan <sanshan.zhang@nxp.com>
Diffstat (limited to 'drivers/crypto')
| -rwxr-xr-x | drivers/crypto/fsl_caam.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/crypto/fsl_caam.c b/drivers/crypto/fsl_caam.c index ee556bd..e9edb67 100755 --- a/drivers/crypto/fsl_caam.c +++ b/drivers/crypto/fsl_caam.c @@ -151,6 +151,14 @@ uint32_t caam_decap_blob(uint32_t plain_text, uint32_t blob_addr, uint32_t size) flush_dcache_range((uint32_t)g_input_ring & ALIGN_MASK, ((uint32_t)g_input_ring & ALIGN_MASK) + 128); + invalidate_dcache_range((uint32_t)decap_dsc & ALIGN_MASK, + ((uint32_t)decap_dsc & ALIGN_MASK) + 128); + invalidate_dcache_range((uint32_t)g_input_ring & ALIGN_MASK, + ((uint32_t)g_input_ring & ALIGN_MASK) + 128); + invalidate_dcache_range((uint32_t)blob_addr & ALIGN_MASK, + (((uint32_t)blob_addr + 2 * size + 64) & ALIGN_MASK)); + invalidate_dcache_range((uint32_t)plain_text & ALIGN_MASK, + (((uint32_t)plain_text + 2 * size + 64) & ALIGN_MASK)); /* Increment jobs added */ __raw_writel(1, CAAM_IRJAR0); @@ -160,6 +168,8 @@ uint32_t caam_decap_blob(uint32_t plain_text, uint32_t blob_addr, uint32_t size) // TODO: check if Secure memory is cacheable. flush_dcache_range((uint32_t)g_output_ring & ALIGN_MASK, ((uint32_t)g_output_ring & ALIGN_MASK) + 128); + invalidate_dcache_range((uint32_t)g_output_ring & ALIGN_MASK, + ((uint32_t)g_output_ring & ALIGN_MASK) + 128); /* check that descriptor address is the one expected in the output ring */ if(g_output_ring[0] == (uint32_t)decap_dsc) { @@ -224,6 +234,9 @@ uint32_t caam_gen_blob(uint32_t plain_data_addr, uint32_t blob_addr, uint32_t si (((uint32_t)blob + 2 * size + 64) & ALIGN_MASK)); flush_dcache_range((uint32_t)g_input_ring & ALIGN_MASK, ((uint32_t)g_input_ring & ALIGN_MASK) + 128); + + invalidate_dcache_range((uint32_t)blob & ALIGN_MASK, + (((uint32_t)blob + 2 * size + 64) & ALIGN_MASK)); /* Increment jobs added */ __raw_writel(1, CAAM_IRJAR0); |