crypto/fsl: SEC driver cleanup for 64 bit and endianness

The SEC driver code has been cleaned up to work for 64 bit
physical addresses and systems where endianess of SEC block
is different from the Core.
Changes:
1. Descriptor created on Core is modified as per SEC block
   endianness before the job is submitted.
2. The read/write of physical addresses to Job Rings will
   be depend on endianness of SEC block as 32 bit low and
   high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in
   descriptor will vary depending on endianness of SEC.

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

1 files changed, 26 insertions, 0 deletions

diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h
index f9cae91..2559ccd 100644
--- a/drivers/crypto/fsl/desc_constr.h
+++ b/drivers/crypto/fsl/desc_constr.h
@@ -36,6 +36,23 @@
 			       LDST_SRCDST_WORD_DECOCTRL | \
 			       (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
 
+#ifdef CONFIG_PHYS_64BIT
+union ptr_addr_t {
+	u64 m_whole;
+	struct {
+#ifdef CONFIG_SYS_FSL_SEC_LE
+		u32 low;
+		u32 high;
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+		u32 high;
+		u32 low;
+#else
+#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
+#endif
+	} m_halfs;
+};
+#endif
+
 static inline int desc_len(u32 *desc)
 {
 	return *desc & HDR_DESCLEN_MASK;
@@ -65,7 +82,16 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
 {
 	dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
 
+#ifdef CONFIG_PHYS_64BIT
+	/* The Position of low and high part of 64 bit address
+	 * will depend on the endianness of CAAM Block */
+	union ptr_addr_t ptr_addr;
+	ptr_addr.m_halfs.high = (u32)(ptr >> 32);
+	ptr_addr.m_halfs.low = (u32)ptr;
+	*offset = ptr_addr.m_whole;
+#else
 	*offset = ptr;
+#endif
 
 	(*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ;
 }