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| author | Thomas Abraham <thomas.ab@samsung.com> | 2016-04-23 22:18:09 +0530 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2016-05-25 10:00:18 +0900 |
| commit | 166097e8775343898cab84f1f23b4aacb35783db (patch) | |
| tree | ff6044c97f1787150e5f5fa66f1734c933cfacae /drivers/clk/exynos/clk-pll.h | |
| parent | 16ca80adc551808b6be1d43f30997f8b4fdfbd39 (diff) | |
| download | u-boot-imx-166097e8775343898cab84f1f23b4aacb35783db.zip u-boot-imx-166097e8775343898cab84f1f23b4aacb35783db.tar.gz u-boot-imx-166097e8775343898cab84f1f23b4aacb35783db.tar.bz2 | |
clk: exynos: add clock driver for Exynos7420 Soc
Add a clock driver for Exynos7420 SoC. There are about 25 clock controller
blocks in Exynos7420 out of which support for topc, top0 and peric1 blocks
are added in this initial version of the driver.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'drivers/clk/exynos/clk-pll.h')
| -rw-r--r-- | drivers/clk/exynos/clk-pll.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h new file mode 100644 index 0000000..631d035 --- /dev/null +++ b/drivers/clk/exynos/clk-pll.h @@ -0,0 +1,9 @@ +/* + * Exynos PLL helper functions for clock drivers. + * Copyright (C) 2016 Samsung Electronics + * Thomas Abraham <thomas.ab@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq); |