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| author | Simon Glass <sjg@chromium.org> | 2015-01-19 22:16:13 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-01-24 06:13:45 -0700 |
| commit | a9aff2f46a7f7d29a662531dbc181773f16a606d (patch) | |
| tree | 4c340ea0b74ccb57fae8987f13b1aae994ef77b3 /drivers/bootcount/bootcount_blackfin.c | |
| parent | 146251f87eaebbd77ca9596391890b44cbda47fb (diff) | |
| download | u-boot-imx-a9aff2f46a7f7d29a662531dbc181773f16a606d.zip u-boot-imx-a9aff2f46a7f7d29a662531dbc181773f16a606d.tar.gz u-boot-imx-a9aff2f46a7f7d29a662531dbc181773f16a606d.tar.bz2 | |
x86: dts: Add SPI flash MRC details for chromebook_link
Correct the SPI flash compatible string, add an alias and specify the
position of the MRC cache, used to store SDRAM training settings for the
Memory Reference Code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/bootcount/bootcount_blackfin.c')
0 files changed, 0 insertions, 0 deletions