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authorAnson Huang <b20788@freescale.com>2012-12-05 13:58:34 -0500
committerJason Liu <r64343@freescale.com>2012-12-13 15:11:43 +0800
commit98a5299c945cb7e440e3c3d9c572f017e5a02ede (patch)
treeb13d402770a2e07e41185ad24870260a39942f9c /drivers/block/sata_dwc.c
parent956ae96db2cdcc6e17f0b28aa97484717957b4c8 (diff)
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ENGR00235821 mx6: correct work flow of PFDsrel_imx_3.0.35_1.1.1rel_imx_3.0.35_1.1.0
PFDs need to be gate/ungate after PLL lock to reset PFDs to right state. Otherwise PFDs may lose correct state in state-machine, then no output clock. For i.MX6DL and i.MX6SL, ROM have taken care of PFD396 already since the bus clock needs it. Signed-off-by: Anson Huang <b20788@freescale.com>
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