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| author | Timur Tabi <timur@freescale.com> | 2011-11-21 17:10:23 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-11-29 08:48:06 -0600 |
| commit | fbc20aab119b70119a2c1db7dfbecb4a6ee0f6a5 (patch) | |
| tree | c0b8dee0c09e028f869aca7a6122967787c02e2b /drivers/block/fsl_sata.c | |
| parent | 3e0529f742e893653848494ffb9f7cd0d91304bf (diff) | |
| download | u-boot-imx-fbc20aab119b70119a2c1db7dfbecb4a6ee0f6a5.zip u-boot-imx-fbc20aab119b70119a2c1db7dfbecb4a6ee0f6a5.tar.gz u-boot-imx-fbc20aab119b70119a2c1db7dfbecb4a6ee0f6a5.tar.bz2 | |
powerpc/85xx: always implement the work-around for Erratum SATA_A001
On the P1022/P1013, the work-around for erratum SATA_A001 was implemented
only if U-Boot initializes SATA, but SATA is not initialized by default. So
move the work-around to the CPU initialization function, so that it's always
executed on the SOCs that need it.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'drivers/block/fsl_sata.c')
| -rw-r--r-- | drivers/block/fsl_sata.c | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index 6b35173..3026ade 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -197,27 +197,6 @@ int init_sata(int dev) /* Wait the controller offline */ ata_wait_register(®->hstatus, HSTATUS_ONOFF, 0, 1000); -#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) - /* - * For P1022/1013 Rev1.0 silicon, after power on SATA host - * controller is configured in legacy mode instead of the - * expected enterprise mode. software needs to clear bit[28] - * of HControl register to change to enterprise mode from - * legacy mode. - */ - { - u32 svr = get_svr(); - if (IS_SVR_REV(svr, 1, 0) && - ((SVR_SOC_VER(svr) == SVR_P1022) || - (SVR_SOC_VER(svr) == SVR_P1022_E) || - (SVR_SOC_VER(svr) == SVR_P1013) || - (SVR_SOC_VER(svr) == SVR_P1013_E))) { - out_le32(®->hstatus, 0x20000000); - out_le32(®->hcontrol, 0x00000100); - } - } -#endif - /* Set the command header base address to CHBA register to tell DMA */ out_le32(®->chba, (u32)cmd_hdr & ~0x3); |