diff options
| author | Jon Loeliger <jdl@freescale.com> | 2005-07-25 14:05:07 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2005-07-25 14:05:07 -0500 |
| commit | d9b94f28a442b0013caef99de084d7b72e2d4607 (patch) | |
| tree | 1b293a551e021a4a696717231ec03206d9f172de /doc | |
| parent | 288693abe1f7c23e69479fd85c2c0d8d7fdbf8f2 (diff) | |
| download | u-boot-imx-d9b94f28a442b0013caef99de084d7b72e2d4607.zip u-boot-imx-d9b94f28a442b0013caef99de084d7b72e2d4607.tar.gz u-boot-imx-d9b94f28a442b0013caef99de084d7b72e2d4607.tar.bz2 | |
* Patch by Jon Loeliger, 2005-05-05
Implemented support for MPC8548CDS board.
Added DDR II support based on SPD values for MPC85xx boards.
This roll-up patch also includes bugfies for the previously
published patches:
DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.mpc85xxads | 9 | ||||
| -rw-r--r-- | doc/README.mpc85xxcds | 43 |
2 files changed, 46 insertions, 6 deletions
diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads index c488f2a..08d6831 100644 --- a/doc/README.mpc85xxads +++ b/doc/README.mpc85xxads @@ -143,6 +143,7 @@ Updated 13-July-2004 Jon Loeliger CONFIG_DDR_ECC only for ECC DDR module CONFIG_DDR_DLL DLL fix on some ADS boards needed for more stability. + CONFIG_HAS_FEC If an FEC is on chip, set to 1, else 0. Other than the above definitions, the rest in the config files are straightforward. @@ -190,10 +191,10 @@ straightforward. 4.4 Reflash U-boot Image using U-boot - => tftp 10000 u-boot.bin - => protect off fff80000 ffffffff - => erase fff80000 ffffffff - => cp.b 10000 fff80000 80000 + tftp 10000 u-boot.bin + protect off fff80000 ffffffff + erase fff80000 ffffffff + cp.b 10000 fff80000 80000 4.5 Reflash U-Boot with a BDI-2000 diff --git a/doc/README.mpc85xxcds b/doc/README.mpc85xxcds index e0f4916..bc5db0c 100644 --- a/doc/README.mpc85xxcds +++ b/doc/README.mpc85xxcds @@ -135,8 +135,8 @@ The default setting of all switches on the carrier board is: SW4=10001000 -CPU Card Switches ------------------ +8555/41 CPU Card Switches +------------------------- Most switches on the CPU Card should not be changed. However, the frequency can be changed by setting SW3: @@ -160,6 +160,45 @@ A safe default setting for all switches on the CPU board is: SW4=11111110 +8548 CPU Card Switches +---------------------- +And, just to be confusing, in this set of switches: + + ON = 1 + OFF = 0 + +Default + SW1=11111101 + SW2=10011111 + SW3=11001000 (8X) (2:1) + SW4=11110011 + + SW3=X000XXXX == CORE:CCB 4:1 + X001XXXX == CORE:CCB 9:2 + X010XXXX == CORE:CCB 1:1 + X011XXXX == CORE:CCB 3:2 + X100XXXX == CORE:CCB 2:1 + X101XXXX == CORE:CCB 5:2 + X110XXXX == CORE:CCB 3:1 + X111XXXX == CORE:CCB 7:2 + XXXX0000 == CCB:SYSCLK 16:1 + XXXX0001 == RESERVED + XXXX0010 == CCB:SYSCLK 2:1 + XXXX0011 == CCB:SYSCLK 3:1 + XXXX0100 == CCB:SYSCLK 4:1 + XXXX0101 == CCB:SYSCLK 5:1 + XXXX0110 == CCB:SYSCLK 6:1 + XXXX0111 == RESERVED + XXXX1000 == CCB:SYSCLK 8:1 + XXXX1001 == CCB:SYSCLK 9:1 + XXXX1010 == CCB:SYSCLK 10:1 + XXXX1011 == RESERVED + XXXX1100 == CCB:SYSCLK 12:1 + XXXX1101 == CCB:SYSCLK 20:1 + XXXX1110 == RESERVED + XXXX1111 == RESERVED + + eDINK Info ---------- |