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authorJon Smirl <jonsmirl@gmail.com>2009-06-14 18:21:28 -0400
committerWolfgang Denk <wd@denx.de>2009-07-10 23:21:32 +0200
commitc9969947a4687de90e2bb58e76842b491aa0e0b9 (patch)
tree7bd09807d9660c477ca5fca8b8e5ca8547f1d008 /doc
parent3672cd5c3b53d219d33345eebad4e25ad5bf6d52 (diff)
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board support patch for phyCORE-MPC5200B-tiny
Add support for the Phytec phyCORE-MPC5200B-tiny. Code originally from Pengutronix.de. Created CONFIG_SYS_ATA_CS_ON_TIMER01 define for when IDE CS is on Timer 0/1 Signed-off-by: Jon Smirl <jonsmirl@gmail.com> Acked-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'doc')
-rw-r--r--doc/README.phytec.pcm03046
1 files changed, 46 insertions, 0 deletions
diff --git a/doc/README.phytec.pcm030 b/doc/README.phytec.pcm030
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+To build RAMBOOT, replace this section the main Makefile
+
+pcm030_config \
+pcm030_RAMBOOT_config \
+pcm030_LOWBOOT_config: unconfig
+ @ >include/config.h
+ @[ -z "$(findstring LOWBOOT_,$@)" ] || \
+ { echo "TEXT_BASE = 0xFF000000" >board/phytec/pcm030/config.tmp ; \
+ echo "... with LOWBOOT configuration" ; \
+ }
+ @[ -z "$(findstring RAMBOOT_,$@)" ] || \
+ { echo "TEXT_BASE = 0x00100000" >board/phycore_mpc5200b_tiny/\
+ config.tmp ; \
+ echo "... with RAMBOOT configuration" ; \
+ echo "... remember to make sure that MBAR is already \
+ switched to 0xF0000000 !!!" ; \
+ }
+ @$(MKCONFIG) -a pcm030 ppc mpc5xxx pcm030 phytec
+ @ echo "remember to set pcm030_REV to 0 for rev 1245.0 rev or to 1 for rev 1245.1"
+
+
+Alternative SDRAM settings:
+
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x715f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+
+/* Settings for XLB = 99 MHz */
+#define SDRAM_MODE 0x008D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x714b0f00
+#define SDRAM_CONFIG1 0x63611730
+#define SDRAM_CONFIG2 0x47670000
+
+The board ships default with the environment in EEPROM
+Moving the environment to flash can be more reliable
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xfe0000)
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_SECT_SIZE 0x20000
+
+
+