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authorStefan Roese <sr@denx.de>2016-01-18 11:55:44 +0100
committerBin Meng <bmeng.cn@gmail.com>2016-01-28 13:53:29 +0800
commit9b5dbe135887cf0853c175780f5b16b3fd0974a4 (patch)
tree70d2d0faa264be47428dd54b78af609375778eec /doc
parentb20c38a973a51bf3f663bd298c63ad1b8e0de445 (diff)
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x86: baytrail: Add documentation for FSP memory-down values
This patch adds the documentation for the memory-down parameters of the Intel FSP. To configure a board without SPD DDR DIMM but with onboard DDR chips. The values are taken from the coreboot header: src/soc/intel/fsp_baytrail/chip.h (git ID da1a70ea from 2016-01-16 as reference). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Andrew Bradford <andrew.bradford@kodakalaris.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'doc')
-rw-r--r--doc/device-tree-bindings/misc/intel,baytrail-fsp.txt31
1 files changed, 30 insertions, 1 deletions
diff --git a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt
index b44b5b5..07fa46e 100644
--- a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt
+++ b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt
@@ -74,12 +74,41 @@ discovered by the FSP and used to setup main memory.
# Integer properties:
- - fsp,dram-speed
+ - fsp,dram-speed:
+ 0x0: "800 MHz"
+ 0x1: "1066 MHz"
+ 0x2: "1333 MHz"
+ 0x3: "1600 MHz"
+
- fsp,dram-type
+ 0x0: "DDR3"
+ 0x1: "DDR3L"
+ 0x2: "DDR3U"
+ 0x4: "LPDDR2"
+ 0x5: "LPDDR3"
+ 0x6: "DDR4"
+
- fsp,dimm-width
+ 0x0: "x8"
+ 0x1: "x16"
+ 0x2: "x32"
+
- fsp,dimm-density
+ 0x0: "1 Gbit"
+ 0x1: "2 Gbit"
+ 0x2: "4 Gbit"
+ 0x3: "8 Gbit"
+
- fsp,dimm-bus-width
+ 0x0: "8 bits"
+ 0x1: "16 bits"
+ 0x2: "32 bits"
+ 0x3: "64 bits"
+
- fsp,dimm-sides
+ 0x0: "1 rank"
+ 0x1: "2 ranks"
+
- fsp,dimm-tcl
- fsp,dimm-trpt-rcd
- fsp,dimm-twr