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author | Tom Rini <trini@ti.com> | 2014-01-09 11:05:32 -0500 |
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committer | Tom Rini <trini@ti.com> | 2014-01-09 11:05:32 -0500 |
commit | 8401bfa91ef57e331e2a3abdf768d41803bec88e (patch) | |
tree | 144e43bb5db26b33fcbadbb52d80760af2f70d04 /doc | |
parent | 33d413fc91e0bbbb92962a80f5333d6f1f628c5b (diff) | |
parent | c5c1af21764d9423b45c1d03e835c4547a8bc5cb (diff) | |
download | u-boot-imx-8401bfa91ef57e331e2a3abdf768d41803bec88e.zip u-boot-imx-8401bfa91ef57e331e2a3abdf768d41803bec88e.tar.gz u-boot-imx-8401bfa91ef57e331e2a3abdf768d41803bec88e.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-mmc
Diffstat (limited to 'doc')
-rw-r--r-- | doc/README.socfpga | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/doc/README.socfpga b/doc/README.socfpga new file mode 100644 index 0000000..cfcbbfe --- /dev/null +++ b/doc/README.socfpga @@ -0,0 +1,53 @@ + +-------------------------------------------- +SOCFPGA Documentation for U-Boot and SPL +-------------------------------------------- + +This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore +based SOCFPGA. To know more about the hardware itself, please refer to +www.altera.com. + + +-------------------------------------------- +socfpga_dw_mmc +-------------------------------------------- +Here are macro and detailed configuration required to enable DesignWare SDMMC +controller support within SOCFPGA + +#define CONFIG_MMC +-> To enable the SD MMC framework support + +#define CONFIG_SDMMC_BASE (SOCFPGA_SDMMC_ADDRESS) +-> The base address of CSR register for DesignWare SDMMC controller + +#define CONFIG_GENERIC_MMC +-> Enable the generic MMC driver + +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 +-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM + +#define CONFIG_DWMMC +-> Enable the common DesignWare SDMMC controller framework + +#define CONFIG_SOCFPGA_DWMMC +-> Enable the SOCFPGA specific driver for DesignWare SDMMC controller + +#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 +-> The FIFO depth for SOCFPGA DesignWare SDMMC controller + +#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 +-> Phase-shifted clock of sdmmc_clk for controller to drive command and data to +the card to meet hold time requirements. SD clock is running at 50MHz and +drvsel is set to shift 135 degrees (3 * 45 degrees). With that, the hold time +is 135 / 360 * 20ns = 7.5ns. + +#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 +-> Phase-shifted clock of sdmmc_clk used to sample the command and data from +the card + +#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4 +-> Bus width of data line which either 1, 4 or 8 and based on board routing. + +#define CONFIG_SOCFPGA_DWMMC_BUS_HZ 50000000 +-> The clock rate to controller. Do note the controller have a wrapper which +divide the clock from PLL by 4. |