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authorTom Rini <trini@ti.com>2014-04-25 14:53:51 -0400
committerTom Rini <trini@ti.com>2014-04-25 14:53:51 -0400
commit080d897585428d0fd42c237abfb6746908f4effc (patch)
treedc65d6d4bbbf1a7f06bbb045a981270a7624ec67 /doc
parentadcdeacc3eda1e5949e54062aa99c299e12483be (diff)
parent08ad9b068afb8842df4cd559c327f54a42811a8d (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'doc')
-rw-r--r--doc/README.b4860qds36
-rw-r--r--doc/README.t4240qds53
2 files changed, 89 insertions, 0 deletions
diff --git a/doc/README.b4860qds b/doc/README.b4860qds
index 3da77d9..eada0c7 100644
--- a/doc/README.b4860qds
+++ b/doc/README.b4860qds
@@ -328,3 +328,39 @@ The below commands apply to both B4860QDS and B4420QDS.
On Linux the interfaces are renamed as:
. eth2 -> fm1-gb2
. eth3 -> fm1-gb3
+
+NAND boot with 2 Stage boot loader
+----------------------------------
+PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
+SPL further initialise DDR using SPD and environment variables and copy
+u-boot(768 KB) from flash to DDR.
+Finally SPL transer control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+ Run time view of SPL framework during boot :-
+ -----------------------------------------------
+ Area | Address |
+-----------------------------------------------
+ Secure boot | 0xFFFC0000 (32KB) |
+ headers | |
+ -----------------------------------------------
+ GD, BD | 0xFFFC8000 (4KB) |
+ -----------------------------------------------
+ ENV | 0xFFFC9000 (8KB) |
+ -----------------------------------------------
+ HEAP | 0xFFFCB000 (30KB) |
+ -----------------------------------------------
+ STACK | 0xFFFD8000 (22KB) |
+ -----------------------------------------------
+ U-boot SPL | 0xFFFD8000 (160KB) |
+ -----------------------------------------------
+
+NAND Flash memory Map on B4860 and B4420QDS
+------------------------------------------
+ Start End Definition Size
+0x000000 0x0FFFFF u-boot 1MB
+0x140000 0x15FFFF u-boot env 128KB
+0x1A0000 0x1BFFFF FMAN Ucode 128KB
diff --git a/doc/README.t4240qds b/doc/README.t4240qds
index a9841fb..ef8c75f 100644
--- a/doc/README.t4240qds
+++ b/doc/README.t4240qds
@@ -120,3 +120,56 @@ The override voltage takes effect when booting.
Note: voltage adjustment needs to be done step by step. Changing voltage too
rapidly may cause current surge. The voltage stepping is done by software.
Users can set the final voltage directly.
+
+2-stage NAND/SD boot loader
+-------------------------------
+PBL initializes the internal SRAM and copy SPL(160K) in SRAM.
+SPL further initialise DDR using SPD and environment variables
+and copy u-boot(768 KB) from NAND/SD device to DDR.
+Finally SPL transers control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area | Address |
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB) |
+-------------------------------------------------
+|GD, BD | 0xFFFC8000 (4KB) |
+-------------------------------------------------
+|ENV | 0xFFFC9000 (8KB) |
+-------------------------------------------------
+|HEAP | 0xFFFCB000 (50KB) |
+-------------------------------------------------
+|STACK | 0xFFFD8000 (22KB) |
+-------------------------------------------------
+|U-boot SPL | 0xFFFD8000 (160KB) |
+-------------------------------------------------
+
+NAND Flash memory Map on T4QDS
+--------------------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot img 1MB
+0x140000 0x15FFFF u-boot env 128KB
+0x160000 0x17FFFF FMAN Ucode 128KB
+
+Micro SD Card memory Map on T4QDS
+----------------------------------------------------
+Block #blocks Definition Size
+0x008 2048 u-boot img 1MB
+0x800 0016 u-boot env 8KB
+0x820 0128 FMAN ucode 64KB
+
+Switch Settings: (ON is 1, OFF is 0)
+===============
+NAND boot SW setting:
+SW1[1:8] = 10000010
+SW2[1.1] = 0
+SW6[1:4] = 1001
+
+SD boot SW setting:
+SW1[1:8] = 00100000
+SW2[1.1] = 0