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author | Tom Rini <trini@ti.com> | 2014-11-24 12:00:00 -0500 |
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committer | Tom Rini <trini@ti.com> | 2014-11-24 12:00:00 -0500 |
commit | 746667f1e56bf08d03e66a178df3c4f4f6c806e1 (patch) | |
tree | e42c7fd72cb1ef97a5a05a73b06b3cd2fc118147 /doc | |
parent | 6c016485a685b5cdac28edb25147311a3e88d51f (diff) | |
parent | fe5b9b447c6eea3873833b1f3ba15c9854aa2ef8 (diff) | |
download | u-boot-imx-746667f1e56bf08d03e66a178df3c4f4f6c806e1.zip u-boot-imx-746667f1e56bf08d03e66a178df3c4f4f6c806e1.tar.gz u-boot-imx-746667f1e56bf08d03e66a178df3c4f4f6c806e1.tar.bz2 |
Merge git://git.denx.de/u-boot-x86
Conflicts:
arch/x86/cpu/Makefile
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'doc')
-rw-r--r-- | doc/device-tree-bindings/misc/intel-lpc.txt | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/misc/intel-lpc.txt b/doc/device-tree-bindings/misc/intel-lpc.txt new file mode 100644 index 0000000..7e1b389 --- /dev/null +++ b/doc/device-tree-bindings/misc/intel-lpc.txt @@ -0,0 +1,23 @@ +Intel LPC Device Binding +======================== + +The device tree node which describes the operation of the Intel Low Pin +Count device is as follows: + +Required properties : +- compatible = "intel,lpc" +- gen-dec : Specifies the values for the gen-dec registers. Up to four cell + pairs can be provided - the first of each pair is the base address and + the second is the size. These are written into the GENx_DEC registers of + the LPC device + + +Example +------- + +lpc { + compatible = "intel,lpc"; + #address-cells = <1>; + #size-cells = <1>; + gen-dec = <0x800 0xfc 0x900 0xfc>; +}; |