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authorTom Rini <trini@ti.com>2014-11-24 12:00:00 -0500
committerTom Rini <trini@ti.com>2014-11-24 12:00:00 -0500
commit746667f1e56bf08d03e66a178df3c4f4f6c806e1 (patch)
treee42c7fd72cb1ef97a5a05a73b06b3cd2fc118147 /doc
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parentfe5b9b447c6eea3873833b1f3ba15c9854aa2ef8 (diff)
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Merge git://git.denx.de/u-boot-x86
Conflicts: arch/x86/cpu/Makefile Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'doc')
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+Intel LPC Device Binding
+========================
+
+The device tree node which describes the operation of the Intel Low Pin
+Count device is as follows:
+
+Required properties :
+- compatible = "intel,lpc"
+- gen-dec : Specifies the values for the gen-dec registers. Up to four cell
+ pairs can be provided - the first of each pair is the base address and
+ the second is the size. These are written into the GENx_DEC registers of
+ the LPC device
+
+
+Example
+-------
+
+lpc {
+ compatible = "intel,lpc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ gen-dec = <0x800 0xfc 0x900 0xfc>;
+};