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authorSimon Glass <sjg@chromium.org>2014-11-14 18:18:38 -0700
committerSimon Glass <sjg@chromium.org>2014-11-25 06:34:01 -0700
commit3ac839352db2fb464e1e6e6a4bc50f06fb29cdb0 (patch)
treefc4597857ff5299dbbb4abeb752ad3027000655b /doc
parent05efc3961cf01916b32ef58a3965d46a11636e68 (diff)
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x86: ivybridge: Add SATA init
Add code to set up the SATA interfaces on boot. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'doc')
-rw-r--r--doc/device-tree-bindings/ata/intel-sata.txt26
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diff --git a/doc/device-tree-bindings/ata/intel-sata.txt b/doc/device-tree-bindings/ata/intel-sata.txt
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+Intel Pantherpoint SATA Device Binding
+======================================
+
+The device tree node which describes the operation of the Intel Pantherpoint
+SATA device is as follows:
+
+Required properties :
+- compatible = "intel,pantherpoint-ahci"
+- intel,sata-mode : string, one of:
+ "ahci" : Use AHCI mode (default)
+ "combined" : Use combined IDE + legacy mode
+ "plain-ide" : Use plain IDE mode
+- intel,sata-port-map : Which SATA ports are enabled, bit 0=enable first port,
+ bit 1=enable second port, etc.
+- intel,sata-port0-gen3-tx : Value for the IOBP_SP0G3IR register
+- intel,sata-port1-gen3-tx : Value for the IOBP_SP1G3IR register
+
+Example
+-------
+
+sata {
+ compatible = "intel,pantherpoint-ahci";
+ intel,sata-mode = "ahci";
+ intel,sata-port-map = <1>;
+ intel,sata-port0-gen3-tx = <0x00880a7f>;
+};