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authorwdenk <wdenk>2004-01-03 19:43:48 +0000
committerwdenk <wdenk>2004-01-03 19:43:48 +0000
commitc935d3bd8b1c7f681ad58e64bd0548e1b26a7d2f (patch)
tree2529369b185098e6d38627b7500d7450d9bab8f5 /doc
parent3a473b2a6523db9cdf2b5aed22d9730b4ebc5693 (diff)
downloadu-boot-imx-c935d3bd8b1c7f681ad58e64bd0548e1b26a7d2f.zip
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Patches by Stephan Linz, 11 Dec 2003:
- more documentation for NIOS port - new struct nios_pio_t, struct nios_spi_t - Reconfiguration for NIOS Development Kit DK1C20: o move board related code from board/dk1c20 to board/altera/dk1c20 o create a new common source path board/altera/common and move generic flash access stuff into it o change/expand configuration file DK1C20.h - Add support for NIOS Development Kit DK1S10 - Add status LED support for NIOS systems - Add dual 7-segment LED support for Altera NIOS DevKits
Diffstat (limited to 'doc')
-rw-r--r--doc/README.dk1c20_std32365
-rw-r--r--doc/README.dk1s10_std32353
-rw-r--r--doc/README.dk1s40_std32355
-rw-r--r--doc/README.dk20k200_std32242
-rw-r--r--doc/README.nios98
-rw-r--r--doc/README.nios_CFG_NIOS_CPU140
-rw-r--r--doc/README.nios_DK192
7 files changed, 1729 insertions, 16 deletions
diff --git a/doc/README.dk1c20_std32 b/doc/README.dk1c20_std32
new file mode 100644
index 0000000..4822c6f
--- /dev/null
+++ b/doc/README.dk1c20_std32
@@ -0,0 +1,365 @@
+
+TODO: specify IDE i/f
+ specify ASMI i/f
+ specify OCI
+
+
+===============================================================================
+ C P U , M E M O R Y , I N / O U T C O M P O N E N T S
+===============================================================================
+see also [1]-[6]
+
+CPU: "standard_32"
+ 32 bit NIOS for 50 MHz
+ 256 Byte for register file (15 levels)
+ 4 KByte instruction cache (2 bytes in each cache line)
+ 4 KByte data cache (4 bytes in each cache line)
+ 2 KByte On Chip ROM with GERMS boot monitor
+ no On Chip RAM
+ MSTEP multiplier
+ no Debug Core
+ On Chip Instrumentation (OCI) enabled
+
+ U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000
+ CFG_NIOS_CPU_ICACHE = 4096
+ CFG_NIOS_CPU_DCACHE = 4096
+ CFG_NIOS_CPU_REG_NUMS = 256
+ CFG_NIOS_CPU_MUL = 0
+ CFG_NIOS_CPU_MSTEP = 1
+ CFG_NIOS_CPU_DBG_CORE = 0
+
+OCI: (TODO)
+
+IRQ: Nr. | used by
+ ------+--------------------------------------------------------
+ 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16
+ 25 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 25
+ 30 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 30
+ 35 | PIO5 | CFG_NIOS_CPU_PIO5_IRQ = 35
+ 40 | PIO0 | CFG_NIOS_CPU_PIO0_IRQ = 40
+ 45 | ASMI | CFG_NIOS_CPU_ASMI0_IRQ = 45
+ 50 | TIMER1 | CFG_NIOS_CPU_TIMER1_IRQ = 50
+
+MEMORY: 8 MByte Flash
+ 1 MByte SRAM
+ 16 MByte SDRAM
+
+ASMI: (TODO) <-- ASMI part is 4M bits
+
+Timer: TIMER0: high priority programmable timer (IRQ16)
+ TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50)
+
+ U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 1
+ CFG_NIOS_CPU_USER_TIMER = 0
+
+PIO: Nr. | description
+ ------+--------------------------------------------------------
+ PIO0 | BUTTON: 4 inputs for user push buttons (IRQ40)
+ PIO1 | LCD: 11 in/outputs for ASCII LCD
+ PIO2 | LED: 8 outputs for user LEDs
+ PIO3 | SEVENSEG: 16 outputs for user seven segment display
+ PIO4 | RECONF: 1 in/output for . . . . . . . . . . . .
+ PIO5 | CFPRESENT: 1 input for CF present event (IRQ35)
+ PIO6 | CFPOWER: 1 output to controll CF power supply
+ PIO7 | CFATASEL: 1 output to controll CF ATA card select
+
+ U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 0
+ CFG_NIOS_CPU_LCD_PIO = 1
+ CFG_NIOS_CPU_LED_PIO = 2
+ CFG_NIOS_CPU_SEVENSEG_PIO = 3
+ CFG_NIOS_CPU_RECONF_PIO = 4
+ CFG_NIOS_CPU_CFPRESENT_PIO = 5
+ CFG_NIOS_CPU_CFPOWER_PIO = 6
+ CFG_NIOS_CPU_CFATASEL_PIO = 7
+
+UART: UART0: fixed baudrate of 115200, fixed protocol 8N1,
+ without handshake RTS/CTS (IRQ25)
+
+LAN: SMsC LAN91C111 with:
+ - offset 0x300 (LAN91C111_REGISTERS_OFFSET)
+ - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)
+
+IDE: (TODO)
+
+
+===============================================================================
+ M E M O R Y M A P
+===============================================================================
+
+- - - - - - - - - - - external memory 2 - - - - - - - - - - - - - - - - - - -
+
+ 0x02000000 ---32-----------16|15------------0-
+ | : | \
+ | : | |
+ SDRAM | : | > CFG_NIOS_CPU_SRAM_SIZE
+ | : | | = 0x01000000
+ | : | /
+ 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE
+ | |
+ : gap :
+ : :
+
+- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
+
+ : :
+ : gap :
+ | |
+ 0x________ ---32-----------16|15------------0-
+ | | | \
+ : (real size : : |
+ ASMI i/f : and content : : > 0x________
+ [5] : unknown) : : |
+ | | | /
+ 0x00920b00 ---32-----------16|15------------0- CFG_NIOS_CPU_ASMI0
+ | |
+ : gap :
+ | |
+ 0x00920a80 ---32-----------16|15------------0-
+ | | | \
+ : (real size : : |
+ IDE i/f : and content : : > 0x00000080
+ [6] : unknown) : : |
+ | | | /
+ 0x00920a00 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0
+ | (unused) | \
+ + 0x1c |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x18 |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x14 |- - - - - - - - - - - - - - - -| |
+ TIMER1 | (unused) | |
+ [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
+ | (unused) | |
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x08 |- - - - - - - - - - - - - - - -| |
+ | control (1 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | status (2 bit) (rw) | /
+ 0x009209e0 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER1
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO7 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (wo) | /
+ 0x009209d0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO7
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO6 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (wo) | /
+ 0x009209c0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO6
+ | edgecapture (1 bit) (rw) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO5 | interruptmask (1 bit) (rw) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (ro) | /
+ 0x009209b0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO5
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO4 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | direction (1 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (rw) | /
+ 0x009209a0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO4
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO3 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (16 bit) (wo) | /
+ 0x00920990 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO2 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (8 bit) (wo) | /
+ 0x00920980 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO1 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | direction (11 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (11 bit) (rw) | /
+ 0x00920970 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1
+ | edgecapture (4 bit) (rw) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO0 | interruptmask (4 bit) (rw) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (4 bit) (ro) | /
+ 0x00920960 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0
+ | (unused) | \
+ + 0x1c |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x18 |- - - - - - - - - - - - - - - -| |
+ | snaph (16 bit) (rw) | |
+ + 0x14 |- - - - - - - - - - - - - - - -| |
+ TIMER0 | snapl (16 bit) (rw) | |
+ [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
+ | periodh (16 bit) (rw) | |
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ | periodl (16 bit) (rw) | |
+ + 0x08 |- - - - - - - - - - - - - - - -| |
+ | control (4 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | status (2 bit) (rw) | /
+ 0x00920940 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0
+ | | \
+ : gap : > (space for UART1)
+ | | /
+ 0x00920920 ---32-----------16|15------------0-
+ | (unused) | \
+ + 0x1c |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x18 |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x14 |- - - - - - - - - - - - - - - -| |
+ UART0 | (unused) | > 0x00000020
+ [2] + 0x10 |- - - - - - - - - - - - - - - -| |
+ | control (10 bit) (rw) | |
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ | status (10 bit) (rw) | |
+ + 0x08 |- - - - - - - - - - - - - - - -| |
+ | txdata (8 bit) (wo) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | rxdata (8 bit) (ro) | /
+ 0x00920900 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0
+
+- - - - - - - - - - - on chip debugging - - - - - - - - - - - - - - - - - - -
+
+ 0x00920900 -----------------------------------
+ | | \
+ : (real size : |
+ OCI Debug : and content : > CFG_NIOS_CPU_OCI_SIZE
+ : unknown) : | = 0x00000100
+ | | /
+ 0x00920800 ----------------------------------- CFG_NIOS_CPU_OCI_BASE
+
+- - - - - - - - - - - on chip memory - - - - - - - - - - -
+
+ 0x00920800 ---32-----------16|15------------0-
+ | : | \
+ | : | |
+ GERMS | : | > CFG_NIOS_CPU_ROM_SIZE
+ | : | | = 0x00000800
+ | : | /
+ 0x00920000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT
+ 0x00920000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE
+
+- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - -
+
+ 0x00920000 ---32-----------16|15------------0-
+ | gap | \
+ 0x00910310 --+-------------------------------| |
+ | | |
+ | register bank (size = 0x10) | |
+ | +--------.---.---.--- | |
+ | | bank 0 \ 1 \ 2 \ 3 \ | |
+ | |---------------------------+ | |
+ LAN91C111 | | BANK | RESERVED | | |
+ | |- - - - - - -|- - - - - - -| | > na_lan91c111_size
+ | | RPCR | MIR | | | = 0x00010000
+ | |- - - - - - -|- - - - - - -| | |
+ | | COUNTER | RCR | | |
+ | |- - - - - - -|- - - - - - -| | |
+ | | EPH STATUS | TCR | | |
+ | +---------------------------+ | |
+ 0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| |
+ | gap | /
+ 0x00910000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE
+ | |
+ : gap :
+ : :
+
+- - - - - - - - - - - external memory 1 - - - - - - - - - - - - - - - - - - -
+
+ : :
+ : gap :
+ | |
+ 0x00900000 ---32-----------16|15------------0-
+ 0x00900000 --+32-----------16|15------------0+
+ | : | \ \
+ | : | | |
+ | : | | > CFG_NIOS_CPU_VEC_SIZE
+ | : | | | = 0x00000100
+ | : | | /
+ 0x008fff00 |- - - - - - - -:- - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE
+ 0x008fff00 |- - - - - - - -:- - - - - - - -+-|- CFG_NIOS_CPU_STACK
+ | : | | \
+ | : | | |
+ | : | | > stack area
+ | : | | |
+ | : | | V
+ | : | |
+ SRAM | : | > CFG_NIOS_CPU_SRAM_SIZE
+ | : | | = 0x00100000
+ | : | /
+ 0x00800000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE
+ 0x00800000 ---8-------------4|3-------------0-
+ | sector 127 | \
+ + 0x7f0000 |- - - - - - - - - - - - - - - -| |
+ | : | |
+ Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE
+ | sector 1 : | | = 0x00800000
+ + 0x010000 |- - - - - - - - - - - - - - - -| |
+ | sector 0 (size = 0x10000) | /
+ 0x00000000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE
+
+
+===============================================================================
+ F L A S H M E M O R Y A L L O C A T I O N
+===============================================================================
+
+ 0x00800000 ---8-------------4|3-------------0-
+ | : | \
+ SAFE | : | > 1 MByte
+ FPGA conf. | : | / (NOT usable by software)
+ 0x00700000 --+- - - - - - - -:- - - - - - - -+-
+ | : | \
+ USER | : | > 1 MByte
+ FPGA conf. | : | / (NOT usable by software)
+ 0x00600000 --+- - - - - - - -:- - - - - - - -+-
+ | : | \
+ | : | |
+ WEB pages | : | > 2 MByte
+ | : | | (provisory usable)
+ | : | /
+ 0x00400000 --+- - - - - - - -:- - - - - - - -+-
+ | : | \
+ | : | |
+ | : | |
+ | : | > 4 MByte free for use
+ | : | |
+ 0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
+ | : | /
+ 0x00000000 ---8-------------4|3-------------0-
+
+
+===============================================================================
+ R E F E R E N C E S
+===============================================================================
+[1] http://www.altera.com/literature/manual/mnl_nios_board_cyclone_1c20.pdf
+[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
+[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
+[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
+[5] http://www.altera.com/literature/ds/ds_nios_asmi.pdf
+ http://www.altera.com/literature/wp/wp_epcs_cyc.pdf
+[6] http://www.opencores.org/projects/ata/
+ http://www.t13.org/index.html
+
+
+===============================================================================
+Stephan Linz <linz@li-pro.net>
diff --git a/doc/README.dk1s10_std32 b/doc/README.dk1s10_std32
new file mode 100644
index 0000000..33ae15e
--- /dev/null
+++ b/doc/README.dk1s10_std32
@@ -0,0 +1,353 @@
+
+TODO: specify IDE i/f
+ specify OCI
+
+
+===============================================================================
+ C P U , M E M O R Y , I N / O U T C O M P O N E N T S
+===============================================================================
+see also [1]-[5]
+
+CPU: "standard_32"
+ 32 bit NIOS for 50 MHz
+ 256 Byte for register file (15 levels)
+ 4 KByte instruction cache (4 bytes in each cache line)
+ 4 KByte data cache (4 bytes in each cache line)
+ 2 KByte On Chip ROM with GERMS boot monitor
+ 64 KByte On Chip RAM
+ MSTEP multiplier
+ no Debug Core
+ On Chip Instrumentation (OCI) enabled
+
+ U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000
+ CFG_NIOS_CPU_ICACHE = 4096
+ CFG_NIOS_CPU_DCACHE = 4096
+ CFG_NIOS_CPU_REG_NUMS = 256
+ CFG_NIOS_CPU_MUL = 0
+ CFG_NIOS_CPU_MSTEP = 1
+ CFG_NIOS_CPU_DBG_CORE = 0
+
+OCI: (TODO)
+
+IRQ: Nr. | used by
+ ------+--------------------------------------------------------
+ 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16
+ 25 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 25
+ 30 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 30
+ 35 | PIO5 | CFG_NIOS_CPU_PIO5_IRQ = 35
+ 40 | PIO0 | CFG_NIOS_CPU_PIO0_IRQ = 40
+ 50 | TIMER1 | CFG_NIOS_CPU_TIMER1_IRQ = 50
+
+MEMORY: 8 MByte Flash
+ 1 MByte SRAM
+ 16 MByte SDRAM
+
+Timer: TIMER0: high priority programmable timer (IRQ16)
+ TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50)
+
+ U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 1
+ CFG_NIOS_CPU_USER_TIMER = 0
+
+PIO: Nr. | description
+ ------+--------------------------------------------------------
+ PIO0 | BUTTON: 4 inputs for user push buttons (IRQ40)
+ PIO1 | LCD: 11 in/outputs for ASCII LCD
+ PIO2 | LED: 8 outputs for user LEDs
+ PIO3 | SEVENSEG: 16 outputs for user seven segment display
+ PIO4 | RECONF: 1 in/output for . . . . . . . . . . . .
+ PIO5 | CFPRESENT: 1 input for CF present event (IRQ35)
+ PIO6 | CFPOWER: 1 output to controll CF power supply
+ PIO7 | CFATASEL: 1 output to controll CF ATA card select
+
+ U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 0
+ CFG_NIOS_CPU_LCD_PIO = 1
+ CFG_NIOS_CPU_LED_PIO = 2
+ CFG_NIOS_CPU_SEVENSEG_PIO = 3
+ CFG_NIOS_CPU_RECONF_PIO = 4
+ CFG_NIOS_CPU_CFPRESENT_PIO = 5
+ CFG_NIOS_CPU_CFPOWER_PIO = 6
+ CFG_NIOS_CPU_CFATASEL_PIO = 7
+
+UART: UART0: fixed baudrate of 115200, fixed protocol 8N1,
+ without handshake RTS/CTS (IRQ25)
+
+LAN: SMsC LAN91C111 with:
+ - offset 0x300 (LAN91C111_REGISTERS_OFFSET)
+ - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)
+
+IDE: (TODO)
+
+
+===============================================================================
+ M E M O R Y M A P
+===============================================================================
+
+- - - - - - - - - - - external memory 2 - - - - - - - - - - - - - - - - - - -
+
+ 0x02000000 ---32-----------16|15------------0-
+ | : | \
+ | : | |
+ SDRAM | : | > CFG_NIOS_CPU_SRAM_SIZE
+ | : | | = 0x01000000
+ | : | /
+ 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE
+ | |
+ : gap :
+ : :
+
+- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
+
+ : :
+ : gap :
+ | |
+ 0x00920a80 ---32-----------16|15------------0-
+ | | | \
+ : (real size : : |
+ IDE i/f : and content : : > 0x00000080
+ [5] : unknown) : : |
+ | | | /
+ 0x00920a00 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0
+ | (unused) | \
+ + 0x1c |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x18 |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x14 |- - - - - - - - - - - - - - - -| |
+ TIMER1 | (unused) | |
+ [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
+ | (unused) | |
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x08 |- - - - - - - - - - - - - - - -| |
+ | control (1 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | status (2 bit) (rw) | /
+ 0x009209e0 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER1
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO7 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (wo) | /
+ 0x009209d0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO7
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO6 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (wo) | /
+ 0x009209c0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO6
+ | edgecapture (1 bit) (rw) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO5 | interruptmask (1 bit) (rw) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (ro) | /
+ 0x009209b0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO5
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO4 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | direction (1 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (rw) | /
+ 0x009209a0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO4
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO3 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (16 bit) (wo) | /
+ 0x00920990 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO2 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (8 bit) (wo) | /
+ 0x00920980 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO1 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | direction (11 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (11 bit) (rw) | /
+ 0x00920970 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1
+ | edgecapture (4 bit) (rw) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO0 | interruptmask (4 bit) (rw) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (4 bit) (ro) | /
+ 0x00920960 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0
+ | (unused) | \
+ + 0x1c |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x18 |- - - - - - - - - - - - - - - -| |
+ | snaph (16 bit) (rw) | |
+ + 0x14 |- - - - - - - - - - - - - - - -| |
+ TIMER0 | snapl (16 bit) (rw) | |
+ [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
+ | periodh (16 bit) (rw) | |
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ | periodl (16 bit) (rw) | |
+ + 0x08 |- - - - - - - - - - - - - - - -| |
+ | control (4 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | status (2 bit) (rw) | /
+ 0x00920940 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0
+ | | \
+ : gap : > (space for UART1)
+ | | /
+ 0x00920920 ---32-----------16|15------------0-
+ | (unused) | \
+ + 0x1c |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x18 |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x14 |- - - - - - - - - - - - - - - -| |
+ UART0 | (unused) | > 0x00000020
+ [2] + 0x10 |- - - - - - - - - - - - - - - -| |
+ | control (10 bit) (rw) | |
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ | status (10 bit) (rw) | |
+ + 0x08 |- - - - - - - - - - - - - - - -| |
+ | txdata (8 bit) (wo) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | rxdata (8 bit) (ro) | /
+ 0x00920900 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0
+
+- - - - - - - - - - - on chip debugging - - - - - - - - - - - - - - - - - - -
+
+ 0x00920900 -----------------------------------
+ | | \
+ : (real size : |
+ OCI Debug : and content : > CFG_NIOS_CPU_OCI_SIZE
+ : unknown) : | = 0x00000100
+ | | /
+ 0x00920800 ----------------------------------- CFG_NIOS_CPU_OCI_BASE
+
+- - - - - - - - - - - on chip memory 2 - - - - - - - - - - -
+
+ 0x00920800 ---32-----------16|15------------0-
+ | : | \
+ | : | |
+ GERMS | : | > CFG_NIOS_CPU_ROM_SIZE
+ | : | | = 0x00000800
+ | : | /
+ 0x00920000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT
+ 0x00920000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE
+
+- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - -
+
+ 0x00920000 ---32-----------16|15------------0-
+ | gap | \
+ 0x00910310 --+-------------------------------| |
+ | | |
+ | register bank (size = 0x10) | |
+ | +--------.---.---.--- | |
+ | | bank 0 \ 1 \ 2 \ 3 \ | |
+ | |---------------------------+ | |
+ LAN91C111 | | BANK | RESERVED | | |
+ | |- - - - - - -|- - - - - - -| | > na_lan91c111_size
+ | | RPCR | MIR | | | = 0x00010000
+ | |- - - - - - -|- - - - - - -| | |
+ | | COUNTER | RCR | | |
+ | |- - - - - - -|- - - - - - -| | |
+ | | EPH STATUS | TCR | | |
+ | +---------------------------+ | |
+ 0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| |
+ | gap | /
+ 0x00910000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE
+
+- - - - - - - - - - - on chip memory 1 - - - - - - - - - - -
+
+ 0x00910000 ---32-----------16|15------------0-
+ | : | \
+ | : | |
+ onchip RAM | : | > CFG_NIOS_CPU_RAM_SIZE
+ | : | | = 0x00010000
+ | : | /
+ 0x00900000 ---32-----------16|15------------0- CFG_NIOS_CPU_RAM_BASE
+
+- - - - - - - - - - - external memory 1 - - - - - - - - - - - - - - - - - - -
+
+ 0x00900000 ---32-----------16|15------------0-
+ 0x00900000 --+32-----------16|15------------0+
+ | . | \ \
+ | . | | |
+ | . | | > CFG_NIOS_CPU_VEC_SIZE
+ | . | | | = 0x00000100
+ | . | | /
+ 0x008fff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE
+ 0x008fff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_STACK
+ | . | | \
+ | . | | |
+ | . | | > stack area
+ | . | | |
+ | . | | V
+ | . | |
+ SRAM | . | > CFG_NIOS_CPU_SRAM_SIZE
+ | . | | = 0x00100000
+ | | /
+ 0x00800000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE
+ 0x00800000 ---8-------------4|3-------------0-
+ | sector 127 | \
+ + 0x7f0000 |- - - - - - - - - - - - - - - -| |
+ | : | |
+ Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE
+ | sector 1 : | | = 0x00800000
+ + 0x010000 |- - - - - - - - - - - - - - - -| |
+ | sector 0 (size = 0x10000) | /
+ 0x00000000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE
+
+
+===============================================================================
+ F L A S H M E M O R Y A L L O C A T I O N
+===============================================================================
+
+ 0x00800000 ---8-------------4|3-------------0-
+ | : | \
+ SAFE | : | > 1 MByte
+ FPGA conf. | : | / (NOT usable by software)
+ 0x00700000 --+- - - - - - - -:- - - - - - - -+-
+ | : | \
+ USER | : | > 1 MByte
+ FPGA conf. | : | / (NOT usable by software)
+ 0x00600000 --+- - - - - - - -:- - - - - - - -+-
+ | : | \
+ | : | |
+ WEB pages | : | > 2 MByte
+ | : | | (provisory usable)
+ | : | /
+ 0x00400000 --+- - - - - - - -:- - - - - - - -+-
+ | : | \
+ | : | |
+ | : | |
+ | : | > 4 MByte free for use
+ | : | |
+ 0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
+ | : | /
+ 0x00000000 ---8-------------4|3-------------0-
+
+
+===============================================================================
+ R E F E R E N C E S
+===============================================================================
+[1] http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s10.pdf
+[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
+[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
+[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
+[5] http://www.opencores.org/projects/ata/
+ http://www.t13.org/index.html
+
+
+===============================================================================
+Stephan Linz <linz@li-pro.net>
diff --git a/doc/README.dk1s40_std32 b/doc/README.dk1s40_std32
new file mode 100644
index 0000000..08c8244
--- /dev/null
+++ b/doc/README.dk1s40_std32
@@ -0,0 +1,355 @@
+
+TODO: specify IDE i/f
+ specify OCI
+
+
+===============================================================================
+ C P U , M E M O R Y , I N / O U T C O M P O N E N T S
+===============================================================================
+see also [1]-[5]
+
+CPU: "standard_32"
+ 32 bit NIOS for 50 MHz
+ 256 Byte for register file (15 levels)
+ 4 KByte instruction cache (4 bytes in each cache line)
+ 4 KByte data cache (4 bytes in each cache line)
+ 2 KByte On Chip ROM with GERMS boot monitor
+ 64 KByte On Chip RAM
+ MSTEP multiplier
+ no Debug Core
+ On Chip Instrumentation (OCI) enabled
+
+ U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000
+ CFG_NIOS_CPU_ICACHE = 4096
+ CFG_NIOS_CPU_DCACHE = 4096
+ CFG_NIOS_CPU_REG_NUMS = 256
+ CFG_NIOS_CPU_MUL = 0
+ CFG_NIOS_CPU_MSTEP = 1
+ CFG_NIOS_CPU_DBG_CORE = 0
+
+OCI: (TODO)
+
+IRQ: Nr. | used by
+ ------+--------------------------------------------------------
+ 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16
+ 25 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 25
+ 30 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 30
+ 35 | PIO5 | CFG_NIOS_CPU_PIO5_IRQ = 35
+ 40 | PIO0 | CFG_NIOS_CPU_PIO0_IRQ = 40
+ 50 | TIMER1 | CFG_NIOS_CPU_TIMER1_IRQ = 50
+
+MEMORY: 8 MByte Flash
+ 1 MByte SRAM
+ 16 MByte SDRAM
+
+Timer: TIMER0: high priority programmable timer (IRQ16)
+ TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50)
+
+ U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 1
+ CFG_NIOS_CPU_USER_TIMER = 0
+
+PIO: Nr. | description
+ ------+--------------------------------------------------------
+ PIO0 | BUTTON: 4 inputs for user push buttons (IRQ40)
+ PIO1 | LCD: 11 in/outputs for ASCII LCD
+ PIO2 | LED: 8 outputs for user LEDs
+ PIO3 | SEVENSEG: 16 outputs for user seven segment display
+ PIO4 | RECONF: 1 in/output for . . . . . . . . . . . .
+ PIO5 | CFPRESENT: 1 input for CF present event (IRQ35)
+ PIO6 | CFPOWER: 1 output to controll CF power supply
+ PIO7 | CFATASEL: 1 output to controll CF ATA card select
+
+ U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 0
+ CFG_NIOS_CPU_LCD_PIO = 1
+ CFG_NIOS_CPU_LED_PIO = 2
+ CFG_NIOS_CPU_SEVENSEG_PIO = 3
+ CFG_NIOS_CPU_RECONF_PIO = 4
+ CFG_NIOS_CPU_CFPRESENT_PIO = 5
+ CFG_NIOS_CPU_CFPOWER_PIO = 6
+ CFG_NIOS_CPU_CFATASEL_PIO = 7
+
+UART: UART0: fixed baudrate of 115200, fixed protocol 8N1,
+ without handshake RTS/CTS (IRQ25)
+
+LAN: SMsC LAN91C111 with:
+ - offset 0x300 (LAN91C111_REGISTERS_OFFSET)
+ - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)
+
+IDE: (TODO)
+
+
+===============================================================================
+ M E M O R Y M A P
+===============================================================================
+
+- - - - - - - - - - - external memory 2 - - - - - - - - - - - - - - - - - - -
+
+ 0x02000000 ---32-----------16|15------------0-
+ | : | \
+ | : | |
+ SDRAM | : | > CFG_NIOS_CPU_SRAM_SIZE
+ | : | | = 0x01000000
+ | : | /
+ 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE
+ | |
+ : gap :
+ : :
+
+- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
+
+ : :
+ : gap :
+ | |
+ 0x00920a80 ---32-----------16|15------------0-
+ | | | \
+ : (real size : : |
+ IDE i/f : and content : : > 0x00000080
+ [5] : unknown) : : |
+ | | | /
+ 0x00920a00 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0
+ | (unused) | \
+ + 0x1c |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x18 |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x14 |- - - - - - - - - - - - - - - -| |
+ TIMER1 | (unused) | |
+ [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
+ | (unused) | |
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x08 |- - - - - - - - - - - - - - - -| |
+ | control (1 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | status (2 bit) (rw) | /
+ 0x009209e0 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER1
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO7 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (wo) | /
+ 0x009209d0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO7
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO6 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (wo) | /
+ 0x009209c0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO6
+ | edgecapture (1 bit) (rw) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO5 | interruptmask (1 bit) (rw) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (ro) | /
+ 0x009209b0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO5
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO4 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | direction (1 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (1 bit) (rw) | /
+ 0x009209a0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO4
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO3 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (16 bit) (wo) | /
+ 0x00920990 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO2 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (8 bit) (wo) | /
+ 0x00920980 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO1 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | direction (11 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (11 bit) (rw) | /
+ 0x00920970 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1
+ | edgecapture (4 bit) (rw) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO0 | interruptmask (4 bit) (rw) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (4 bit) (ro) | /
+ 0x00920960 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0
+ | (unused) | \
+ + 0x1c |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x18 |- - - - - - - - - - - - - - - -| |
+ | snaph (16 bit) (rw) | |
+ + 0x14 |- - - - - - - - - - - - - - - -| |
+ TIMER0 | snapl (16 bit) (rw) | |
+ [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
+ | periodh (16 bit) (rw) | |
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ | periodl (16 bit) (rw) | |
+ + 0x08 |- - - - - - - - - - - - - - - -| |
+ | control (4 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | status (2 bit) (rw) | /
+ 0x00920940 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0
+ | | \
+ : gap : > (space for UART1)
+ | | /
+ 0x00920920 ---32-----------16|15------------0-
+ | (unused) | \
+ + 0x1c |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x18 |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x14 |- - - - - - - - - - - - - - - -| |
+ UART0 | (unused) | > 0x00000020
+ [2] + 0x10 |- - - - - - - - - - - - - - - -| |
+ | control (10 bit) (rw) | |
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ | status (10 bit) (rw) | |
+ + 0x08 |- - - - - - - - - - - - - - - -| |
+ | txdata (8 bit) (wo) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | rxdata (8 bit) (ro) | /
+ 0x00920900 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0
+
+- - - - - - - - - - - on chip debugging - - - - - - - - - - - - - - - - - - -
+
+ 0x00920900 -----------------------------------
+ | | \
+ : (real size : |
+ OCI Debug : and content : > CFG_NIOS_CPU_OCI_SIZE
+ : unknown) : | = 0x00000100
+ | | /
+ 0x00920800 ----------------------------------- CFG_NIOS_CPU_OCI_BASE
+
+- - - - - - - - - - - on chip memory 2 - - - - - - - - - - -
+
+ 0x00920800 ---32-----------16|15------------0-
+ | : | \
+ | : | |
+ GERMS | : | > CFG_NIOS_CPU_ROM_SIZE
+ | : | | = 0x00000800
+ | : | /
+ 0x00920000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT
+ 0x00920000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE
+
+- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - -
+
+ 0x00920000 ---32-----------16|15------------0-
+ | gap | \
+ 0x00910310 --+-------------------------------| |
+ | | |
+ | register bank (size = 0x10) | |
+ | +--------.---.---.--- | |
+ | | bank 0 \ 1 \ 2 \ 3 \ | |
+ | |---------------------------+ | |
+ LAN91C111 | | BANK | RESERVED | | |
+ | |- - - - - - -|- - - - - - -| | > na_lan91c111_size
+ | | RPCR | MIR | | | = 0x00010000
+ | |- - - - - - -|- - - - - - -| | |
+ | | COUNTER | RCR | | |
+ | |- - - - - - -|- - - - - - -| | |
+ | | EPH STATUS | TCR | | |
+ | +---------------------------+ | |
+ 0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| |
+ | gap | /
+ 0x00910000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE
+
+- - - - - - - - - - - on chip memory 1 - - - - - - - - - - -
+
+ 0x00910000 ---32-----------16|15------------0-
+ | : | \
+ | : | |
+ onchip RAM | : | > CFG_NIOS_CPU_RAM_SIZE
+ | : | | = 0x00010000
+ | : | /
+ 0x00900000 ---32-----------16|15------------0- CFG_NIOS_CPU_RAM_BASE
+
+- - - - - - - - - - - external memory 1 - - - - - - - - - - - - - - - - - - -
+
+ 0x00900000 ---32-----------16|15------------0-
+ 0x00900000 --+32-----------16|15------------0+
+ | . | \ \
+ | . | | |
+ | . | | > CFG_NIOS_CPU_VEC_SIZE
+ | . | | | = 0x00000100
+ | . | | /
+ 0x008fff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE
+ 0x008fff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_STACK
+ | . | | \
+ | . | | |
+ | . | | > stack area
+ | . | | |
+ | . | | V
+ | . | |
+ SRAM | . | > CFG_NIOS_CPU_SRAM_SIZE
+ | . | | = 0x00100000
+ | | /
+ 0x00800000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE
+ 0x00800000 ---8-------------4|3-------------0-
+ | sector 127 | \
+ + 0x7f0000 |- - - - - - - - - - - - - - - -| |
+ | : | |
+ Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE
+ | sector 1 : | | = 0x00800000
+ + 0x010000 |- - - - - - - - - - - - - - - -| |
+ | sector 0 (size = 0x10000) | /
+ 0x00000000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE
+
+
+===============================================================================
+ F L A S H M E M O R Y A L L O C A T I O N
+===============================================================================
+
+ 0x00800000 ---8-------------4|3-------------0-
+ | : | \
+ | : | |
+ SAFE | : | > 2 MByte
+ FPGA conf. | : | | (NOT usable by software)
+ | : | /
+ 0x00600000 --+- - - - - - - -:- - - - - - - -+-
+ | : | \
+ | : | |
+ USER | : | > 2 MByte
+ FPGA conf. | : | | (NOT usable by software)
+ | : | /
+ 0x00400000 --+- - - - - - - -:- - - - - - - -+-
+ | : | \
+ | : | |
+ WEB pages | : | > 2 MByte
+ | : | | (provisory usable)
+ | : | /
+ 0x00200000 --+- - - - - - - -:- - - - - - - -+-
+ | : | \
+ | : | |
+ | : | > 2 MByte free for use
+ 0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
+ | : | /
+ 0x00000000 ---8-------------4|3-------------0-
+
+
+===============================================================================
+ R E F E R E N C E S
+===============================================================================
+[1] http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s40.pdf
+[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
+[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
+[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
+[5] http://www.opencores.org/projects/ata/
+ http://www.t13.org/index.html
+
+
+===============================================================================
+Stephan Linz <linz@li-pro.net>
diff --git a/doc/README.dk20k200_std32 b/doc/README.dk20k200_std32
new file mode 100644
index 0000000..2c2b1d6
--- /dev/null
+++ b/doc/README.dk20k200_std32
@@ -0,0 +1,242 @@
+
+===============================================================================
+ C P U , M E M O R Y , I N / O U T C O M P O N E N T S
+===============================================================================
+see also [1]-[4]
+
+CPU: "standard_32"
+ 32 bit NIOS for 33.333 MHz (nasys_clock_freq = 33333000)
+ 256 Byte for register file (15 levels)
+ no instruction cache
+ no data cache
+ 1 KByte On Chip ROM with GERMS boot monitor
+ no On Chip RAM
+ MSTEP multiplier
+ no Debug Core
+ no On Chip Instrumentation (OCI) enabled
+
+ U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000
+ CFG_NIOS_CPU_ICACHE = 0
+ CFG_NIOS_CPU_DCACHE = 0
+ CFG_NIOS_CPU_REG_NUMS = 256
+ CFG_NIOS_CPU_MUL = 0
+ CFG_NIOS_CPU_MSTEP = 1
+ CFG_NIOS_CPU_DBG_CORE = 0
+
+IRQ: Nr. | used by
+ ------+--------------------------------------------------------
+ 25 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 25
+ 26 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 26
+ 27 | PIO2 | CFG_NIOS_CPU_PIO2_IRQ = 27
+ 28 | UART1 | CFG_NIOS_CPU_UART1_IRQ = 28 (debug)
+
+MEMORY: 1 MByte Flash
+ 256 KByte SRAM
+ (SDRAM with standard SODIMM only)
+
+Timer: TIMER0: high priority programmable timer (IRQ25)
+
+ U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 0
+
+PIO: Nr. | description
+ ------+--------------------------------------------------------
+ PIO0 | SEVENSEG: 16 outputs for user seven segment display
+ PIO1 | LED: 8 outputs for user LEDs
+ PIO2 | BUTTON: 4 inputs for user push buttons (IRQ27)
+ PIO3 | LCD: 11 in/outputs for ASCII LCD
+
+ U-Boot CFG: CFG_NIOS_CPU_SEVENSEG_PIO = 0
+ CFG_NIOS_CPU_LED_PIO = 1
+ CFG_NIOS_CPU_BUTTON_PIO = 2
+ CFG_NIOS_CPU_LCD_PIO = 3
+
+UART: UART0: fixed baudrate of 115200, fixed protocol 8N2,
+ without handshake RTS/CTS (IRQ26)
+ UART1: fixed baudrate of 115200, fixed protocol 8N1,
+ without handshake RTS/CTS (IRQ28)
+
+
+===============================================================================
+ M E M O R Y M A P
+===============================================================================
+
+- - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - -
+
+ 0x00200000 ---15------------8|7-------------0-
+ | sector 18 | \
+ + 0x0f0000 |- - - - - - - - - - - - - - - -| |
+ | : | |
+ Flash |- - - - : - - - -| |
+ | sector 5 : | |
+ + 0x020000 |- - - - - - - - -| |
+ | sector 4 (size = 0x10000) | |
+ + 0x010000 |- - - - - - - - - - - - - - - -| > CFG_NIOS_CPU_FLASH_SIZE
+ | sector 3 (size = 0x08000) | | = 0x00100000
+ + 0x008000 |- - - - - - - - - - - - - - - -| |
+ | sector 2 (size = 0x02000) | |
+ + 0x006000 |- - - - - - - - - - - - - - - -| |
+ | sector 1 (size = 0x02000) | |
+ + 0x004000 |- - - - - - - - - - - - - - - -| |
+ | sector 0 (size = 0x04000) | /
+ 0x00100000 ---15------------8|7-------------0- CFG_NIOS_CPU_FLASH_BASE
+ | |
+ : gap :
+ | |
+ 0x00080000 ---32-----------16|15------------0-
+ 0x00080000 --+32-----------16|15------------0+
+ | . | \ \
+ | . | | |
+ | . | | > CFG_NIOS_CPU_VEC_SIZE
+ | . | | | = 0x00000100
+ | . | | /
+ 0x0007ff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE
+ 0x0007ff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_STACK
+ | . | | \
+ | . | | |
+ | . | | > stack area
+ | . | | |
+ | . | | V
+ | . | |
+ SRAM | . | > CFG_NIOS_CPU_SRAM_SIZE
+ | . | | = 0x00040000
+ | | /
+ 0x00040000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE
+ | |
+ : gap :
+ : :
+
+- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
+
+ : :
+ : gap :
+ | |
+ 0x00000400 ---32-----------16|15------------0-
+ | (unused) | \
+ + 0x1c |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x18 |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x14 |- - - - - - - - - - - - - - - -| |
+ UART0 | (unused) | > 0x00000020
+ [2] + 0x10 |- - - - - - - - - - - - - - - -| |
+ | control (10 bit) (rw) | |
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ | status (10 bit) (rw) | |
+ + 0x08 |- - - - - - - - - - - - - - - -| |
+ | txdata (8 bit) (wo) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | rxdata (8 bit) (ro) | /
+ 0x000004c0 ---32-----------16|15------------0- CFG_NIOS_CPU_UART1
+ | |
+ : gap :
+ | |
+ 0x00000490 ---32-----------16|15------------0-
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO3 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | direction (11 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (11 bit) (rw) | /
+ 0x00000480 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3
+ | edgecapture (12 bit) (rw) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO2 | interruptmask (12 bit) (rw) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (12 bit) (ro) | /
+ 0x00000470 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO1 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | direction (2 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (2 bit) (rw) | /
+ 0x00000460 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1
+ | (unused) | \
+ + 0x1c |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x18 |- - - - - - - - - - - - - - - -| |
+ | snaph (16 bit) (rw) | |
+ + 0x14 |- - - - - - - - - - - - - - - -| |
+ TIMER0 | snapl (16 bit) (rw) | |
+ [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
+ | periodh (16 bit) (rw) | |
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ | periodl (16 bit) (rw) | |
+ + 0x08 |- - - - - - - - - - - - - - - -| |
+ | control (4 bit) (rw) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | status (2 bit) (rw) | /
+ 0x00000440 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0
+ | (unused) | \
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ PIO0 | (unused) | |
+ [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
+ | (unused) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | data (16 bit) (wo) | /
+ 0x00000420 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0
+ | (unused) | \
+ + 0x1c |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x18 |- - - - - - - - - - - - - - - -| |
+ | (unused) | |
+ + 0x14 |- - - - - - - - - - - - - - - -| |
+ UART0 | (unused) | > 0x00000020
+ [2] + 0x10 |- - - - - - - - - - - - - - - -| |
+ | control (10 bit) (rw) | |
+ + 0x0c |- - - - - - - - - - - - - - - -| |
+ | status (10 bit) (rw) | |
+ + 0x08 |- - - - - - - - - - - - - - - -| |
+ | txdata (8 bit) (wo) | |
+ + 0x04 |- - - - - - - - - - - - - - - -| |
+ | rxdata (8 bit) (ro) | /
+ 0x00000400 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0
+
+- - - - - - - - - - - on chip memory - - - - - - - - - - -
+
+ 0x00000400 ---32-----------16|15------------0-
+ | : | \
+ | : | |
+ GERMS | : | > na_boot_monitor_rom_size
+ | : | | = 0x00000400
+ | : | /
+ 0x00000000 |- - - - - - - - - - - - - - - -+- - nasys_reset_address
+ 0x00000000 ---32-----------16|15------------0- na_boot_monitor_rom
+
+
+===============================================================================
+ F L A S H M E M O R Y A L L O C A T I O N
+===============================================================================
+
+ 0x00200000 ---15------------8|7-------------0-
+ | : | \
+ SAFE | : | > 256 KByte
+ FPGA conf. | : | / (NOT usable by software)
+ 0x001c0000 --+- - - - - - - -:- - - - - - - -+-
+ | : | \
+ USER | : | > 256 KByte
+ FPGA conf. | : | / (NOT usable by software)
+ 0x00180000 --+- - - - - - - -:- - - - - - - -+-
+ | : | \
+ | : | |
+ | : | > 512 KByte free for use
+ 0x00140000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
+ | : | /
+ 0x00100000 ---15------------8|7-------------0-
+
+
+===============================================================================
+ R E F E R E N C E S
+===============================================================================
+[1] http://www.altera.com/literature/ds/ds_nios_board_apex_20k200e.pdf
+[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
+[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
+[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
+
+
+===============================================================================
+Stephan Linz <linz@li-pro.net>
diff --git a/doc/README.nios b/doc/README.nios
index aee0ecd..8765df7 100644
--- a/doc/README.nios
+++ b/doc/README.nios
@@ -1,12 +1,27 @@
U-Boot for Nios-32
- Last Update: October 15, 2003
+ Last Update: November 30, 2003
====================================================================
This file contains information regarding U-Boot and the Altera
Nios CPU. For information regarding U-Boot and the Nios Development
-Kit, Cyclone Edition (DK-1C20), see doc/README.dk1c20.
+Kits see:
+
+ * Cyclone Edition (DK-1C20), see doc/README.dk1c20
+ * Stratix Edition (DK-1S10), see doc/README.dk1s10 (TODO)
+ * Stratix Edition (DK-1S40), see doc/README.dk1s40 (TODO)
+ * Stratix Edition (DK-20K200), see doc/README.dk20k200 (TODO)
+
+For informations regarding Nios Development Kit hardware overview
+and the NIOS CPU standard configuration of all known boards made by
+Altera see:
+
+ * Development Kit (DK) hardware overview, see doc/README.nios_DK
+ * NIOS CPU standard_32 at DK-1C20, see doc/README.dk1c20_std32
+ * NIOS CPU standard_32 at DK-1S10, see doc/README.dk1s10_std32
+ * NIOS CPU standard_32 at DK-1S40, see doc/README.dk1s40_std32
+ * NIOS CPU standard_32 at DK-20K200, see doc/README.dk20k200_std32
For those interested in contributing ... see HELP WANTED below.
@@ -50,16 +65,25 @@ structure definitions from the Nios SDK.
2.1 Nios-specific Options/Settings
-----------------------------------
All configuration options/settings that are specific to Nios begin
-with "CONFIG_NIOS_" or "CFG_NIOS_". The following is a list of
-currently defined Nios-specific options/parameters. If any options
-are related to Standard-32 Nios SDK excalibur.h definitions, the
-related definition follows the description).
+with "CONFIG_NIOS_", "CFG_NIOS_", or "CFG_NIOS_CPU_".
+
+The configuration follows a two-stage process. In the first stage
+the NIOS CPU core will defined like defined in Alteras SOPC Builder.
+At this point we use the "CFG_NIOS_CPU_" defines exclusively. For
+more informations about all the definitions you have to setup see
+into current board configurations and doc/README.nios_CFG_NIOS_CPU.
+In second stage we bring the NIOS CPU configuration in relation to
+U-Boot configuration options/settings. The following is a list of
+currently defined Nios-specific options/parameters used inside of
+U-Boot. If any options are related to Standard-32 Nios SDK
+excalibur.h definitions, the related definition follows the
+description).
CONFIG_NIOS -- defined for all Nios-32 boards.
CFG_NIOS_CONSOLE -- the base address of the console UART.
- (standard-32: na_uart1_base).
+ (standard-32: nasys_uart_0 resp. na_uart1_base).
CFG_NIOS_FIXEDBAUD -- defined if the console UART PTF fixed_baud
parameter is set to '1'.
@@ -71,10 +95,11 @@ CFG_NIOS_MULT_MSTEP -- use hardware assisted multiply using the
CFG_NIOS_TMRBASE -- the base address of the timer used to support
xxx_timer routines (e.g. set_timer(), get_timer(), etc.).
- (standard-32: na_lo_priority_timer2_base).
+ (standard-32: nasys_timer_1 resp. na_lo_priority_timer2_base).
CFG_NIOS_TMRIRQ -- the interrupt request (vector number) assigned to
- the timer. (standard-32: na_low_priority_timer2_irq).
+ the timer. (standard-32: nasys_timer_1_irq resp.
+ na_low_priority_timer2_irq).
CFG_NIOS_TMRMS -- the period of the timer in milliseconds.
@@ -105,20 +130,56 @@ is an alias for 'subi %rB,1' that is supported by the assembler
but does not appear in the programmer's manual.
-4. BRAIN DAMAGE
+4. BOOT PROCESS
+---------------
+
+4.1 Boot process over GERMS
+---------------------------
+When the NIOS CPU catch a reset signal it will begin to be running
+code from CFG_NIOS_CPU_RST_VECT. Normally at this place it will
+find the GERMS monitor. That's the case for the generic NIOS CPU
+configuration "standard_32". When the GERMS monitor starts running,
+it performs important system initializations and then looks for
+executable code in flash, using the following steps:
+
+ 1. Examining the two bytes at CFG_NIOS_CPU_FLASH_BASE + 0x04000C.
+ 2. Examining the button 0 on the PIO CFG_NIOS_CPU_BUTTON_PIO.
+ 3. If the button is not pressed and the two bytes contain 'N'
+ and 'i', the monitor executes a CALL to location
+ CFG_NIOS_CPU_FLASH_BASE + 0x040000.
+ 4. If the code is not executed in step 3 or the code returns,
+ then prints an 8-digit version number to STDOUT and waits for
+ user commands from STDIN.
+
+In normal case, for "standard_32", STDIN and STDOUT are the first
+serial port.
+
+4.2 Return to GERMS command line
+--------------------------------
+During the boot process, the GERMS monitor checks for the existence
+of application software in flash memory. If found, the processor
+immediately executes the code. To return program execution to the
+GERMS monitor (that is, avoid running code stored in flash memory):
+
+ 1. Hold down CFG_NIOS_CPU_BUTTON_PIO, button number 0.
+ 2. Press then release the CPU reset button.
+ 3. Release CFG_NIOS_CPU_BUTTON_PIO, button number 0.
+
+
+5. BRAIN DAMAGE
----------------
This section describes some of the unfortunate and avoidable aspects
of working with the Nios CPU ... and some things you can do to
reduce your pain.
-4.1 GERMS doesn't work with Hyperterminal
+5.1 GERMS doesn't work with Hyperterminal
------------------------------------------
GERMS doesn't do CR/LF mapping that is compatible with Hyperterminal
(or minicom) -- geez. Regardless of you opion of Hyperterminal, this
sad design decision is remedied by using U-Boot.
-4.2 cygwin Incompatibility
+5.2 cygwin Incompatibility
---------------------------
The version of cygwin distributed with the nios GNUPro toolchain is
out-of-date and incompatible with the latest cygwin distributions.
@@ -131,7 +192,7 @@ topic).
The solution ... well, you can wait for Altera ... or build as
set of tools for linux.
-4.3 No native gcc
+5.3 No native gcc
------------------
I'm not sure how this one slipped through the cracks ... but it is
a real pain. Basically, if you want to build anything for the native
@@ -140,9 +201,11 @@ and the old version of cygwin makes locating one challenging.
The solution ... same as above. Just download the gcc source from
Altera and build up a set of cross tools for your favorite linux
-distro.
+distro. Anybody who wants to use an already precompiled NIOS cross
+toolchain can it found in the CDK4NIOS project hosted by Source
+Forge at http://cdk4nios.sourceforge.net.
-4.4 Can't build default U-Boot
+5.4 Can't build default U-Boot
-------------------------------
By default, when you build U-Boot you will be building some native
tools along with the target elf, bin, and srec files. Without a
@@ -167,7 +230,7 @@ environment.o: environment.c ../tools/envcrc
BTW, thats a 'zero' ... not the letter 'O'.
-5. HELP WANTED
+6. HELP WANTED
---------------
There are plenty of areas where help is needed. Here's are some ideas
@@ -190,3 +253,6 @@ Regards,
--Scott
<smcnutt@psyent.com>
+
+--Stephan
+<linz@li-pro.net>
diff --git a/doc/README.nios_CFG_NIOS_CPU b/doc/README.nios_CFG_NIOS_CPU
new file mode 100644
index 0000000..e38ed91
--- /dev/null
+++ b/doc/README.nios_CFG_NIOS_CPU
@@ -0,0 +1,140 @@
+
+===============================================================================
+ C F G _ N I O S _ C P U _ * v s . N I O S S D K
+===============================================================================
+
+When ever you have to make a new NIOS CPU configuration you can use this table
+as a reference list to the original NIOS SDK symbols made by Alteras SOPC
+Builder. Look into excalibur.h and excalibur.s in your SDK path cpu_sdk/inc.
+Symbols beginning with a '[ptf]:' are coming from your SOPC sytem description
+(PTF file) in sections WIZARD_SCRIPT_ARGUMENTS or SYSTEM_BUILDER_INFO.
+
+C O R E N I O S S D K [1],[7]
+-------------------------------------------------------------------------------
+CFG_NIOS_CPU_CLK nasys_clock_freq
+CFG_NIOS_CPU_ICACHE nasys_icache_size
+CFG_NIOS_CPU_DCACHE nasys_dcache_size
+CFG_NIOS_CPU_REG_NUMS nasys_nios_num_regs
+CFG_NIOS_CPU_MUL __nios_use_multiply__
+CFG_NIOS_CPU_MSTEP __nios_use_mstep__
+CFG_NIOS_CPU_STACK nasys_stack_top
+CFG_NIOS_CPU_VEC_BASE nasys_vector_table
+CFG_NIOS_CPU_VEC_SIZE nasys_vector_table_size
+CFG_NIOS_CPU_VEC_NUMS
+CFG_NIOS_CPU_RST_VECT nasys_reset_address
+CFG_NIOS_CPU_DBG_CORE nasys_debug_core
+CFG_NIOS_CPU_RAM_BASE na_onchip_ram_64_kbytes
+CFG_NIOS_CPU_RAM_SIZE na_onchip_ram_64_kbytes_size
+CFG_NIOS_CPU_ROM_BASE na_boot_monitor_rom
+CFG_NIOS_CPU_ROM_SIZE na_boot_monitor_rom_size
+CFG_NIOS_CPU_OCI_BASE nasys_oci_core
+CFG_NIOS_CPU_OCI_SIZE
+CFG_NIOS_CPU_SRAM_BASE na_ext_ram nasys_program_mem
+ nasys_data_mem
+CFG_NIOS_CPU_SRAM_SIZE na_ext_ram_size nasys_program_mem_size
+ nasys_data_mem_size
+CFG_NIOS_CPU_SDRAM_BASE na_sdram
+CFG_NIOS_CPU_SDRAM_SIZE na_sdram_size
+CFG_NIOS_CPU_FLASH_BASE na_ext_flash nasys_main_flash
+ nasys_am29lv065d_flash_0
+ nasys_flash_0
+CFG_NIOS_CPU_FLASH_SIZE na_ext_flash_size nasys_main_flash_size
+
+T I M E R N I O S S D K [3]
+-------------------------------------------------------------------------------
+CFG_NIOS_CPU_TIMER_NUMS nasys_timer_count
+CFG_NIOS_CPU_TIMER[0-9] nasys_timer_[0-9]
+CFG_NIOS_CPU_TIMER[0-9]_IRQ nasys_timer_[0-9]_irq
+CFG_NIOS_CPU_TIMER[0-9]_PER [ptf]:period
+ [ptf]:period_units
+ [ptf]:mult
+CFG_NIOS_CPU_TIMER[0-9]_AR [ptf]:always_run
+CFG_NIOS_CPU_TIMER[0-9]_FP [ptf]:fixed_period
+CFG_NIOS_CPU_TIMER[0-9]_SS [ptf]:snapshot
+
+U A R T N I O S S D K [2]
+-------------------------------------------------------------------------------
+CFG_NIOS_CPU_UART_NUMS nasys_uart_count
+CFG_NIOS_CPU_UART[0-9] nasys_uart_[0-9]
+CFG_NIOS_CPU_UART[0-9]_IRQ nasys_uart_[0-9]_irq
+CFG_NIOS_CPU_UART[0-9]_BR [ptf]:baud
+CFG_NIOS_CPU_UART[0-9]_DB [ptf]:data_bits
+CFG_NIOS_CPU_UART[0-9]_SB [ptf]:stop_bits
+CFG_NIOS_CPU_UART[0-9]_PA [ptf]:parity
+CFG_NIOS_CPU_UART[0-9]_HS [ptf]:use_cts_rts
+CFG_NIOS_CPU_UART[0-9]_EOP [ptf]:use_eop_register
+
+P I O N I O S S D K [4]
+-------------------------------------------------------------------------------
+CFG_NIOS_CPU_PIO_NUMS nasys_pio_count
+CFG_NIOS_CPU_PIO[0-9] nasys_pio_[0-9]
+CFG_NIOS_CPU_PIO[0-9]_IRQ nasys_pio_[0-9]_irq
+CFG_NIOS_CPU_PIO[0-9]_BITS [ptf]:Data_Width
+CFG_NIOS_CPU_PIO[0-9]_TYPE [ptf]:has_tri
+ [ptf]:has_out
+ [ptf]:has_in
+CFG_NIOS_CPU_PIO[0-9]_CAP [ptf]:capture
+CFG_NIOS_CPU_PIO[0-9]_EDGE [ptf]:edge_type
+CFG_NIOS_CPU_PIO[0-9]_ITYPE [ptf]:irq_type
+
+S P I N I O S S D K [6]
+-------------------------------------------------------------------------------
+CFG_NIOS_CPU_SPI_NUMS nasys_spi_count
+CFG_NIOS_CPU_SPI[0-9] nasys_spi_[0-9]
+CFG_NIOS_CPU_SPI[0-9]_IRQ nasys_spi_[0-9]_irq
+CFG_NIOS_CPU_SPI[0-9]_BITS [ptf]:databits
+CFG_NIOS_CPU_SPI[0-9]_MA [ptf]:ismaster
+CFG_NIOS_CPU_SPI[0-9]_SLN [ptf]:numslaves
+CFG_NIOS_CPU_SPI[0-9]_TCLK [ptf]:targetclock
+CFG_NIOS_CPU_SPI[0-9]_TDELAY [ptf]:targetdelay
+CFG_NIOS_CPU_SPI[0-9]_* [ptf]:*
+
+I D E N I O S S D K
+-------------------------------------------------------------------------------
+CFG_NIOS_CPU_IDE_NUMS nasys_usersocket_count
+CFG_NIOS_CPU_IDE[0-9] nasys_usersocket_[0-9]
+
+A S M I N I O S S D K [5]
+-------------------------------------------------------------------------------
+CFG_NIOS_CPU_ASMI_NUMS nasys_asmi_count
+CFG_NIOS_CPU_ASMI[0-9] nasys_asmi_[0-9]
+CFG_NIOS_CPU_ASMI[0-9]_IRQ nasys_asmi_[0-9]_irq
+
+E t h e r n e t ( L A N ) N I O S S D K
+-------------------------------------------------------------------------------
+CFG_NIOS_CPU_LAN_NUMS
+CFG_NIOS_CPU_LAN[0-9]_BASE na_lan91c111
+CFG_NIOS_CPU_LAN[0-9]_OFFS LAN91C111_REGISTERS_OFFSET
+CFG_NIOS_CPU_LAN[0-9]_IRQ na_lan91c111_irq
+CFG_NIOS_CPU_LAN[0-9]_BUSW LAN91C111_DATA_BUS_WIDTH
+CFG_NIOS_CPU_LAN[0-9]_TYPE
+
+s y s t e m c o m p o s i n g N I O S S D K
+-------------------------------------------------------------------------------
+CFG_NIOS_CPU_TICK_TIMER (na_low_priority_timer2)
+CFG_NIOS_CPU_USER_TIMER (na_timer1)
+CFG_NIOS_CPU_BUTTON_PIO (na_button_pio)
+CFG_NIOS_CPU_LCD_PIO (na_lcd_pio)
+CFG_NIOS_CPU_LED_PIO (na_led_pio)
+CFG_NIOS_CPU_SEVENSEG_PIO (na_seven_seg_pio)
+CFG_NIOS_CPU_RECONF_PIO (na_reconfig_request_pio)
+CFG_NIOS_CPU_CFPRESENT_PIO (na_cf_present_pio)
+CFG_NIOS_CPU_CFPOWER_PIO (na_cf_power_pio)
+CFG_NIOS_CPU_CFATASEL_PIO (na_cf_ata_select_pio)
+CFG_NIOS_CPU_USER_SPI (na_spi)
+
+
+===============================================================================
+ R E F E R E N C E S
+===============================================================================
+[1] http://www.altera.com/literature/ds/ds_nioscpu.pdf
+[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
+[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
+[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
+[5] http://www.altera.com/literature/ds/ds_nios_asmi.pdf
+[6] http://www.altera.com/literature/ds/ds_nios_spi.pdf
+[7] http://www.altera.com/literature/ds/ds_legacy_sdram_ctrl.pdf
+
+
+===============================================================================
+Stephan Linz <linz@li-pro.net>
diff --git a/doc/README.nios_DK b/doc/README.nios_DK
new file mode 100644
index 0000000..b119d76
--- /dev/null
+++ b/doc/README.nios_DK
@@ -0,0 +1,192 @@
+
+===============================================================================
+ H A R D W A R E O V E R V I E W
+===============================================================================
+===============|===============|===============|===============|===============
+ | DK20K200 | DK1C20 | DK1S10 | DK1S40
+---------------|---------------|---------------|---------------|---------------
+ | | | |
+ Schem. Nr. | Nios Dev.Brd. | P06-08713-00 | P06-08468-01 | P06-09178-00
+ Rev. | pilot. | 01 | 01 | 00
+ Date | 2001/02/06 | 2003/02/20 | 2003/02/14 | 2003/05/14
+[1] | | | |
+===============|===============|===============|===============|===============
+ | | | |
+ FPGA | "APEX" | "Cyclon" | "Stratix" | "Stratix"
+ | EP20K200E | EP1C20 | EP1S10 | EP1S40
+ | | |
+ | (484 FBGA) | (400 FBGA) | (780 FBGA)
+[2],[3],[4] | | |
+---------------|---------------|---------------|---------------|---------------
+ | |
+ Clock (OSC) | 33.333 MHz | 50 MHz
+ | | (with ext. supply)
+ |
+ | PI49FCT3805
+[5] |
+---------------|---------------|---------------|---------------|---------------
+ | |
+ Flash | 1 MByte | 8 MByte
+ | |
+ | AM29LV800BB | AM29LV065DU120REI
+ | 8/16 bit bus | 8 bit bus
+ | 1 chip | 1 chip
+[6],[7] | |
+---------------|---------------|---------------|---------------|---------------
+ | | |
+ serial | no such | 4 MBits | no such
+ Flash | | |
+ | | EPCS4SI8 |
+[8] | | |
+---------------|---------------|---------------|---------------|---------------
+ | |
+ Compact | no such, as | see below: prototype adapter
+ Flash (CF) | module only |
+ | |
+---------------|---------------|---------------|---------------|---------------
+ | |
+ SRAM | 256 KByte | 1 MByte
+ | |
+ | IDT71V016S | IDT71V416S10PH
+ | 32 bit bus | 32 bit bus
+ | 2 chips | 2 chips
+ | interlaced | interlaced
+[9],[10] | |
+---------------|---------------|---------------|---------------|---------------
+ | |
+ SDRAM | SODIMM only | 16 MByte
+ | |
+ | | MT48LC4M32B2TG-7
+ | 64 bit bus | 32 bit bus
+ | | 1 chip
+[11] | |
+===============|===============|===============|===============|===============
+ | |
+ serial I/O | 1 RS232 | 2 RS232
+ | |
+ | LTC1386 | MAX3237CAI
+ | |
+ | port 1: | port 1:
+ | RxD / TxD, | RxD / TxD,
+ | RTS / CTS | RTS / CTS, DTR / DSR, DCD, RI
+ | |
+ | ! ! ! ! ! ! | port 2: | port 2:
+ | RTS/CTS can | RxD / TxD | RxD / TxD
+ | be RxD/TxD | | RTS / CTS, DTR / DSR
+ | of 2nd port | | DCD, RI
+[12],[13] | ! ! ! ! ! ! | |
+---------------|---------------|---------------|---------------|---------------
+ | |
+ Ethernet | no such, as | 1 10BaseT / 100BaseT
+ | module only |
+ | | LAN91C111-NE
+ | | 32 bit bus
+ | | no external EEPROM
+ | | LEDA# for link
+ | | LEDB# for Rx / Tx
+[14] | |
+===============|===============|===============|===============|===============
+ | |
+ user | 8 | no such
+ switches | SW[7..0] |
+ | |
+---------------|---------------|---------------|---------------|---------------
+ |
+ user push | 4
+ buttons | PB[3..0]
+ |
+---------------|---------------|---------------|---------------|---------------
+ | |
+ user LEDs | 2 | 8
+ | LED[1..0] | LED[7..0]
+ | |
+---------------|---------------|---------------|---------------|---------------
+ |
+ user seven | 2
+ segment | HEX[1..0][G..A,DP]
+ |
+===============|===============|===============|===============|===============
+ | |
+ 3.3V proto- | w/o level | no such -- only 5V
+ type adapter | shift buffer |
+ | |
+ | 40 I/O pins |
+ | 1 card sel. |
+ | 1 reset out. |
+ | 1 OSC clock |
+ | 1 CPU clock |
+ | 1 clock out. |
+ | |
+---------------|---------------|---------------|---------------|---------------
+ | |
+ 5V prototype | with level | 2 ports -- both card ports supplied with its
+ adapter | shift buffer | own level shift buffer
+ | |
+ | 40 I/O pins | port 1 & 2:
+ | 1 card sel. | 41 I/O pins
+ | 1 Vee ? ? ? | 1 card select
+ | 1 reset out. | 1 reset output (from dev/board)
+ | 1 OSC clock | 1 OSC clock (from dev/board)
+ | 1 CPU clock | 1 CPU clock (from dev/board)
+ | 1 clock inp. | 1 clock input (to dev/board)
+ | |
+ | | (special) port 1:
+ | | 1 CF select
+ | | 1 CF present
+ | | 1 CF ATA select
+ | | 1 CF power
+ | |
+ | | NOTE: Both card ports are prepared for raw
+ | | IDE working. You can connect such
+ | | devices directly to the 40 pin header.
+ | | The signal PDIAG (passed diagnostic)
+ | | is not connected to any I/O signal.
+ | | Card port 1 is hard wired to the on
+ | | board Copact Flash adapter together
+ | | with all other signals needed by CF
+ | | cards. Hot plug should be working too.
+[15],[16] | |
+===============|===============|===============|===============|===============
+ | |
+ config. CPLD | EPM7064 | EPM7128
+ | |
+ (alternative | decition by | decision by
+ FPGA conf.) | jumper | push button
+ | |
+ | FPGA config. | FPGA config. | FPGA config.
+ | from Flash | from Flash | from Flash
+ | only | and EPCS4 | only
+ | | |
+===============|===============|===============|===============|===============
+===============================================================================
+
+
+===============================================================================
+ R E F E R E N C E S
+===============================================================================
+[1] http://www.altera.com/literature/lit-nio.jsp
+[2] http://www.altera.com/literature/lit-apx.jsp
+[3] http://www.altera.com/literature/lit-cyc.jsp
+[4] http://www.altera.com/literature/lit-stx.jsp
+[5] http://www.pericom.com/pdf/datasheets/PI49FCT3805.pdf
+ http://www.pericom.com/products/clock/psempart.php?productID=PI49FCT3805
+[6] http://www.amd.com/us-en/FlashMemory/ProductInformation/0,,37_1447_1623_1468^1532,00.html
+ http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/21490.pdf
+[7] http://www.amd.com/us-en/FlashMemory/ProductInformation/0,,37_1447_1623_1468^1596,00.html
+ http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/23544b.pdf
+[8] http://www.altera.com/literature/lit-config.html
+ http://preview.altera.com/literature/ds/micron.pdf
+[9] http://www.idt.com/products/pages/Asynchronous_SRAMs-71V016SA.html
+[10] http://www.idt.com/products/pages/Asynchronous_SRAMs-71V416SL.html
+[11] http://www.micron.com/products/dram/sdram/part.aspx?part=MT48LC4M32B2TG-7
+[12] http://www.linear.com/prod/datasheet.html?datasheet=33
+ http://www.linear.com/pdf/1386fa.pdf
+[13] http://www.maxim-ic.com/quick_view2.cfm/qv_pk/1068/ln/en
+ http://pdfserv.maxim-ic.com/en/ds/MAX3222-MAX3241.pdf
+[14] http://www.smsc.com/main/catalog/lan91c111.html
+[15] http://www.t13.org/index.html
+[16] http://www.compactflash.org/faqs/faq.htm
+
+
+===============================================================================
+Stephan Linz <linz@li-pro.net>