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authorYork Sun <yorksun@freescale.com>2012-08-17 08:22:39 +0000
committerAndy Fleming <afleming@freescale.com>2012-08-23 12:16:55 -0500
commita4c66509f1b95884e5753d5a30cf2cf884adb821 (patch)
tree0e6a44b7d2b286afc7bafff558277d51ca182195 /doc
parentfcea30688fd8c47d54473ffd0f551a5e6efc74a0 (diff)
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powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving
Restructure DDR interleaving option to support 3 and 4 DDR controllers for 2-, 3- and 4-way interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'doc')
-rw-r--r--doc/README.fsl-ddr36
1 files changed, 34 insertions, 2 deletions
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index 5e21658..f94b56f 100644
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -1,5 +1,28 @@
-
-Table of interleaving modes supported in cpu/8xxx/ddr/
+Table of interleaving 2-4 controllers
+=====================================
+ +--------------+-----------------------------------------------------------+
+ |Configuration | Memory Controller |
+ | | 1 2 3 4 |
+ |--------------+--------------+--------------+-----------------------------+
+ | Two memory | Not Intlv'ed | Not Intlv'ed | |
+ | complexes +--------------+--------------+ |
+ | | 2-way Intlv'ed | |
+ |--------------+--------------+--------------+--------------+ |
+ | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | |
+ | Three memory +--------------+--------------+--------------+ |
+ | complexes | 2-way Intlv'ed | Not Intlv'ed | |
+ | +-----------------------------+--------------+ |
+ | | 3-way Intlv'ed | |
+ +--------------+--------------+--------------+--------------+--------------+
+ | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed |
+ | Four memory +--------------+--------------+--------------+--------------+
+ | complexes | 2-way Intlv'ed | 2-way Intlv'ed |
+ | +-----------------------------+-----------------------------+
+ | | 4-way Intlv'ed |
+ +--------------+-----------------------------------------------------------+
+
+
+Table of 2-way interleaving modes supported in cpu/8xxx/ddr/
======================================================
+-------------+---------------------------------------------------------+
| | Rank Interleaving |
@@ -56,6 +79,15 @@ The ways to configure the ddr interleaving mode
# superbank
setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
+ # 1KB 3-way interleaving
+ setenv hwconfig "fsl_ddr:ctlr_intlv=3way_1KB"
+
+ # 4KB 3-way interleaving
+ setenv hwconfig "fsl_ddr:ctlr_intlv=3way_4KB"
+
+ # 8KB 3-way interleaving
+ setenv hwconfig "fsl_ddr:ctlr_intlv=3way_8KB"
+
# disable bank (chip-select) interleaving
setenv hwconfig "fsl_ddr:bank_intlv=null"