Merge git://git.denx.de/u-boot

14 files changed, 656 insertions, 31 deletions

diff --git a/doc/DocBook/Makefile b/doc/DocBook/Makefile
index 2f2ddfc..da88b32 100644
--- a/doc/DocBook/Makefile
+++ b/doc/DocBook/Makefile
@@ -8,7 +8,7 @@
 
 include $(TOPDIR)/config.mk
 
-DOCBOOKS :=
+DOCBOOKS := linker_lists.xml stdio.xml
 
 ###
 # The build process is as follows (targets):
diff --git a/doc/DocBook/linker_lists.tmpl b/doc/DocBook/linker_lists.tmpl
new file mode 100644
index 0000000..f197516
--- /dev/null
+++ b/doc/DocBook/linker_lists.tmpl
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN"
+	"http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd" []>
+
+<book id="UBootLGArrays">
+ <bookinfo>
+  <title>The U-Boot Linker-Generated Arrays</title>
+
+  <legalnotice>
+   <para>
+     This documentation is free software; you can redistribute
+     it and/or modify it under the terms of the GNU General Public
+     License as published by the Free Software Foundation; either
+     version 2 of the License, or (at your option) any later
+     version.
+   </para>
+
+   <para>
+     This program is distributed in the hope that it will be
+     useful, but WITHOUT ANY WARRANTY; without even the implied
+     warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+     See the GNU General Public License for more details.
+   </para>
+
+   <para>
+     You should have received a copy of the GNU General Public
+     License along with this program; if not, write to the Free
+     Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+     MA 02111-1307 USA
+   </para>
+
+   <para>
+     For more details see the file COPYING in the source
+     distribution of U-Boot Bootloader.
+   </para>
+  </legalnotice>
+ </bookinfo>
+
+<toc></toc>
+
+  <chapter id="adt">
+     <title>Linker-Generated Arrays</title>
+!Iinclude/linker_lists.h
+  </chapter>
+
+</book>
diff --git a/doc/DocBook/stdio.tmpl b/doc/DocBook/stdio.tmpl
new file mode 100644
index 0000000..4783abb
--- /dev/null
+++ b/doc/DocBook/stdio.tmpl
@@ -0,0 +1,46 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN"
+	"http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd" []>
+
+<book id="UBootSTDIO">
+ <bookinfo>
+  <title>The U-Boot STDIO subsystem</title>
+
+  <legalnotice>
+   <para>
+     This documentation is free software; you can redistribute
+     it and/or modify it under the terms of the GNU General Public
+     License as published by the Free Software Foundation; either
+     version 2 of the License, or (at your option) any later
+     version.
+   </para>
+
+   <para>
+     This program is distributed in the hope that it will be
+     useful, but WITHOUT ANY WARRANTY; without even the implied
+     warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+     See the GNU General Public License for more details.
+   </para>
+
+   <para>
+     You should have received a copy of the GNU General Public
+     License along with this program; if not, write to the Free
+     Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+     MA 02111-1307 USA
+   </para>
+
+   <para>
+     For more details see the file COPYING in the source
+     distribution of U-Boot Bootloader.
+   </para>
+  </legalnotice>
+ </bookinfo>
+
+<toc></toc>
+
+  <chapter id="adt">
+     <title>U-Boot Serial subsystem</title>
+!Idrivers/serial/serial.c
+  </chapter>
+
+</book>
diff --git a/doc/README.VSC3316-3308 b/doc/README.VSC3316-3308
new file mode 100644
index 0000000..925663b
--- /dev/null
+++ b/doc/README.VSC3316-3308
@@ -0,0 +1,43 @@
+This file contains API information of the initialization code written for
+Vitesse cross-point devices, VSC3316 and VSC3308 for board B4860QDS
+
+Author: Shaveta Leekha <shaveta@freescale.com>
+
+About Device:
+=============
+VSC 3316/3308 is a low-power, low-cost asynchronous crosspoint switch capable of data rates upto 11.5Gbps.
+
+VSC3316 has 16 input and 16 output ports whereas VSC3308 has 8 input and 8 output ports. Programming of these devices are performed by two-wire or four-wire serial interface.
+
+Initialization:
+===============
+On reset, VSC devices are in low-power state with all inputs, outputs and connections in an off state.
+First thing required is to program it to interface with either two-wire or four-wire interface.
+In our case the interface is two-wire I2C serial interface. So the value in Interface mode register at address 79.h to be written is 0x02 for two-wire interface. Also for crosspoint connections to be activated, 01.h value need to be written in 75.h (core configuration register).
+
+API Overview:
+=============
+
+	vsc_if_enable(u8 vsc_addr):
+	--------------------------
+		This API programs VSC to interface with either two-wire or four-wire interface. In our case the interface is two-wire I2C serial interface. So the value in Interface mode register at address 79.h to be written is 0x02 for two-wire interface.
+	Parameters:
+		vsc_addr - Address of the VSC device on board.
+
+
+	vsc3316_config(u8 vsc_addr, int con_arr[][2], u8 num_con):
+	---------------------------------------------------------
+	This API configures the VSC3316 device for required connections. Connection through the VSC device requires the inputs and outputs to be properly configured.
+	Connection registers are on page 00. It Configures the selected input and output correctly and join them to make a connection. It also program Input state register, Global input ISE, Global input LOS, Global core control, Output mode register and core control registers etc.
+	vsc3308_config(u8 vsc_addr, int con_arr[][2], u8 num_con) does the essential configurations for VSC3308.
+
+	Parameters:
+		vsc_addr - Address of the VSC device on board.
+		con_arr - connection array
+		num_con - number of connections to be configured
+
+	vsc_wp_config(u8 vsc_addr):
+	--------------------------
+		For crosspoint connections to be activated, 01.h value need to be written in 75.h (core configuration register), which is done by this API.
+	Parameters:
+		vsc_addr - Address of the VSC device on board.
diff --git a/doc/README.commands b/doc/README.commands
index 125f077..923418b 100644
--- a/doc/README.commands
+++ b/doc/README.commands
@@ -15,12 +15,12 @@ help:	 Long description. This is a string
 
 **** Behind the scene ******
 
-The structure created is named with a special prefix (__u_boot_cmd_)
+The structure created is named with a special prefix (__u_boot_list_cmd_)
 and placed by the linker in a special section.
 
 This makes it possible for the final link to extract all commands
 compiled into any object code and construct a static array so the
-command can be found in an array starting at __u_boot_cmd_start.
+command can be found in an array starting at _u_boot_list_cmd__start.
 
 To ensure that the linker does not discard these symbols when linking
 full U-Boot we generate a list of all the commands we have built (based
@@ -33,6 +33,6 @@ If a new board is defined do not forget to define the command section
 by writing in u-boot.lds ($(TOPDIR)/board/boardname/u-boot.lds) these
 3 lines:
 
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
+	.u_boot_list : {
+	#include "u-boot.lst";
+	}
diff --git a/doc/README.ext4 b/doc/README.ext4
index b3ea8b7..b7d0ad3 100644
--- a/doc/README.ext4
+++ b/doc/README.ext4
@@ -1,15 +1,28 @@
 This patch series adds support for ext4 ls,load and write features in uboot
 Journaling is supported for write feature.
 
+To enable support for the ext4 (and ext2) filesystem implementation,
+#define CONFIG_FS_EXT4
+
+If you want write support,
+#define CONFIG_EXT4_WRITE
+
 To Enable ext2 ls and load commands, modify the board specific config file with
 #define CONFIG_CMD_EXT2
+This automatically defines CONFIG_FS_EXT4 for you.
 
 To Enable ext4 ls and load commands, modify the board specific config file with
 #define CONFIG_CMD_EXT4
+This automatically defines CONFIG_FS_EXT4 for you.
 
 To enable ext4 write command, modify the board specific config file with
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
+These automatically define CONFIG_FS_EXT4 and CONFIG_EXT4_WRITE for you.
+
+Also relevant are the generic filesystem commands,
+#define CONFIG_CMD_FS_GENERIC
+This does not automatically enable EXT4 support for you.
 
 Steps to test:
 
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index f94b56f..3992640 100644
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -103,6 +103,11 @@ The ways to configure the ddr interleaving mode
   # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
   setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
 
+  # bank(chip-select) interleaving (auto)
+  setenv hwconfig "fsl_ddr:bank_intlv=auto"
+  This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings
+  on DIMMs.
+
 Memory controller address hashing
 ==================================
 If the DDR controller supports address hashing, it can be enabled by hwconfig.
diff --git a/doc/README.m54418twr b/doc/README.m54418twr
new file mode 100644
index 0000000..f69ae01
--- /dev/null
+++ b/doc/README.m54418twr
@@ -0,0 +1,244 @@
+Freescale MCF54418TWR ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created Mar 22, 2012
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m54418twr/m54418twr.c	Dram setup
+- board/freescale/m54418twr/Makefile	Makefile
+- board/freescale/m54418twr/config.mk	config make
+- board/freescale/m54418twr/u-boot.lds	Linker description
+
+- arch/m68k/cpu/mcf5445x/cpu.c		cpu specific code
+- arch/m68k/cpu/mcf5445x/cpu_init.c	Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
+- arch/m68k/cpu/mcf5445x/interrupts.c	cpu specific interrupt support
+- arch/m68k/cpu/mcf5445x/speed.c	system, pci, flexbus, and cpu clock
+- arch/m68k/cpu/mcf5445x/Makefile	Makefile
+- arch/m68k/cpu/mcf5445x/config.mk	config make
+- arch/m68k/cpu/mcf5445x/start.S	start up assembly code
+
+- doc/README.m54418twr			This readme file
+
+- drivers/net/mcffec.c			ColdFire common FEC driver
+- drivers/net/mcfmii.c			ColdFire common MII driver
+- drivers/serial/mcfuart.c		ColdFire common UART driver
+
+- arch/m68k/include/asm/bitops.h	Bit operation function export
+- arch/m68k/include/asm/byteorder.h	Byte order functions
+- arch/m68k/include/asm/fec.h		FEC structure and definition
+- arch/m68k/include/asm/global_data.h	Global data structure
+- arch/m68k/include/asm/immap.h		ColdFire specific header file and driver macros
+- arch/m68k/include/asm/immap_5441x.h	mcf5441x specific header file
+- arch/m68k/include/asm/io.h		io functions
+- arch/m68k/include/asm/m5441x.h	mcf5441x specific header file
+- arch/m68k/include/asm/posix_types.h	Posix
+- arch/m68k/include/asm/processor.h	header file
+- arch/m68k/include/asm/ptrace.h	Exception structure
+- arch/m68k/include/asm/rtc.h		Realtime clock header file
+- arch/m68k/include/asm/string.h	String function export
+- arch/m68k/include/asm/timer.h		Timer structure and definition
+- arch/m68k/include/asm/types.h		Data types definition
+- arch/m68k/include/asm/uart.h		Uart structure and definition
+- arch/m68k/include/asm/u-boot.h	u-boot structure
+
+- include/configs/M54418TWR.h		Board specific configuration file
+
+- arch/m68k/lib/board.c			board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts.c		Coldfire common interrupt functions
+- arch/m68k/lib/time.c			Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c			Exception init code
+
+1 MCF5441x specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M54418TWR Development Board
+CONFIG_MCF5441x			-- define for all MCF5441x CPUs
+CONFIG_M54418			-- define for all Freescale MCF54418 CPUs
+CONFIG_M54418TWR		-- define for M54418TWR board
+
+CONFIG_MCFUART			-- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT		-- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE			-- define UART baudrate
+
+CONFIG_MCFFEC			-- define to use common CF FEC driver
+CONFIG_MII			-- enable to use MII driver
+CONFIG_SYS_DISCOVER_PHY		-- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER	-- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN	--
+CONFIG_SYS_FEC0_PINMUX		-- Set FEC0 Pin configuration
+CONFIG_SYS_FEC1_PINMUX		-- Set FEC1 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE		-- Set FEC0 MII base register
+CONFIG_SYS_FEC1_MIIBASE		-- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP		-- set FEC timeout loop
+CONFIG_HAS_ETH1			-- define to enable second FEC in u-boot
+
+CONFIG_MCFTMR			-- define to use DMA timer
+
+CONFIG_SYS_IMMR			-- define for MBAR offset
+
+CONFIG_EXTRA_CLOCK		-- Enable extra clock such as vco, flexbus, pci, etc
+
+CONFIG_SYS_MBAR			-- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM 	-- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR	-- defines the base address of the MCF54455 internal SRAM
+
+CONFIG_SYS_CSn_BASE		-- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK		-- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL		-- defines the Chip Select Control register
+
+CONFIG_SYS_SDRAM_BASE		-- defines the DRAM Base
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+	MRAM:		0x00000000-0x0003FFFF (256KB)
+	DDR:		0x40000000-0x47FFFFFF (128MB)
+	SRAM:		0x80000000-0x8000FFFF (64KB)
+	IP:		0xE0000000-0xFFFFFFFF (512MB)
+
+3. COMPILATION
+==============
+3.1	To create U-Boot the gcc-4.x compiler set (ColdFire ELF version)
+from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+   export CROSS_COMPILE=cross-compile-prefix
+   cd u-boot
+   make distclean
+   make M54418TWR_config, or			- default to spi serial flash boot, 50Mhz input clock
+   make M54418TWR_nand_mii_config, or		- default to nand flash boot, mii mode, 25Mhz input clock
+   make M54418TWR_nand_rmii_config, or		- default to nand flash boot, rmii mode, 50Mhz input clock
+   make M54418TWR_nand_rmii_lowfreq_config, or	- default to nand flash boot, rmii mode, 50Mhz input clock
+   make M54418TWR_serial_mii_config, or		- default to spi serial flash boot, 25Mhz input clock
+   make M54418TWR_serial_rmii_config, or	- default to spi serial flash boot, 50Mhz input clock
+   make
+
+4. SCREEN DUMP
+==============
+4.1 M54418TWR Development board
+    Boot from NAND flash (NOTE: May not show exactly the same)
+
+U-Boot 2012.10-00209-g12ae1d8-dirty (Oct 18 2012 - 15:54:54)
+
+CPU:   Freescale MCF54418 (Mask:a3 Version:1)
+       CPU CLK 250 MHz BUS CLK 125 MHz FLB CLK 125 MHz
+       INP CLK 50 MHz VCO CLK 500 MHz
+Board: Freescale MCF54418 Tower System
+SPI:   ready
+DRAM:  128 MiB
+NAND:  256 MiB
+In:    serial
+Out:   serial
+Err:   serial
+Net:   FEC0, FEC1
+-> pri
+baudrate=115200
+bootargs=root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(k
+ernel)ro,-(jffs2) console=ttyS0,115200
+bootdelay=2
+eth1addr=00:e0:0c:bc:e5:61
+ethact=FEC0
+ethaddr=00:e0:0c:bc:e5:60
+fileaddr=40010000
+filesize=27354
+gatewayip=192.168.1.1
+hostname=M54418TWR
+inpclk=50000000
+ipaddr=192.168.1.2
+load=tftp ${loadaddr} ${u-boot};
+loadaddr=0x40010000
+mem=129024k
+netdev=eth0
+netmask=255.255.255.0
+prog=nand device 0;nand erase 0 40000;nb_update ${loadaddr} ${filesize};save
+serverip=192.168.1.1
+stderr=serial
+stdin=serial
+stdout=serial
+u-boot=u-boot.bin
+upd=run load; run prog
+
+Environment size: 653/131068 bytes
+-> bdinfo
+memstart    = 0x40000000
+memsize     = 0x08000000
+flashstart  = 0x00000000
+flashsize   = 0x00000000
+flashoffset = 0x00000000
+sramstart   = 0x80000000
+sramsize    = 0x00010000
+mbar        = 0xFC000000
+cpufreq     =    250 MHz
+busfreq     =    125 MHz
+flbfreq     =    125 MHz
+inpfreq     =     50 MHz
+vcofreq     =    500 MHz
+ethaddr     = 00:e0:0c:bc:e5:60
+eth1addr    = 00:e0:0c:bc:e5:61
+ip_addr     = 192.168.1.2
+baudrate    = 115200 bps
+-> help
+?       - alias for 'help'
+base    - print or set address offset
+bdinfo  - print Board Info structure
+boot    - boot default, i.e., run 'bootcmd'
+bootd   - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm   - boot application image from memory
+bootp   - boot image via network using BOOTP/TFTP protocol
+bootvx  - Boot vxWorks from an ELF image
+cmp     - memory compare
+coninfo - print console devices and information
+cp      - memory copy
+crc32   - checksum calculation
+dcache  - enable or disable data cache
+dhcp    - boot image via network using DHCP/TFTP protocol
+echo    - echo args to console
+editenv - edit environment variable
+env     - environment handling commands
+exit    - exit script
+false   - do nothing, unsuccessfully
+go      - start application at address 'addr'
+help    - print command description/usage
+icache  - enable or disable instruction cache
+iminfo  - print header information for application image
+imxtract- extract a part of a multi-image
+itest   - return true/false on integer compare
+loop    - infinite loop on address range
+md      - memory display
+mdio    - MDIO utility commands
+mii     - MII utility commands
+mm      - memory modify (auto-incrementing address)
+mtest   - simple RAM read/write test
+mw      - memory write (fill)
+nand    - NAND sub-system
+nb_update- Nand boot update  program
+nboot   - boot from NAND device
+nfs     - boot image via network using NFS protocol
+nm      - memory modify (constant address)
+ping    - send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+reginfo - print register information
+reset   - Perform RESET of the CPU
+run     - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv  - set environment variables
+sf      - SPI flash sub-system
+showvar - print local hushshell variables
+sleep   - delay execution for some time
+source  - run script from memory
+sspi    - SPI utility command
+test    - minimal test like /bin/sh
+tftpboot- boot image via network using TFTP protocol
+true    - do nothing, successfully
+version - print monitor, compiler and linker version
diff --git a/doc/README.mpc85xx-spin-table b/doc/README.mpc85xx-spin-table
new file mode 100644
index 0000000..8da768a
--- /dev/null
+++ b/doc/README.mpc85xx-spin-table
@@ -0,0 +1,26 @@
+Spin table in cache
+=====================================
+As specified by ePAPR v1.1, the spin table needs to be in cached memory. After
+DDR is initialized and U-boot relocates itself into DDR, the spin table is
+accessible for core 0. It is part of release.S, within 4KB range after
+__secondary_start_page. For other cores to use the spin table, the booting
+process is described below:
+
+Core 0 sets up the reset page on the top 4K of memory (or 4GB if total memory
+is more than 4GB), and creates a TLB to map it to 0xffff_f000, regardless of
+the physical address of this page, with WIMGE=0b01010. Core 0 also enables boot
+page translation for secondary cores to use this page of memory. Then 4KB
+memory is copied from __secondary_start_page to the boot page, after flusing
+cache because this page is mapped as normal DDR. Before copying the reset page,
+core 0 puts the physical address of the spin table (which is in release.S and
+relocated to the top of mapped memory) into a variable __spin_table_addr so
+that secondary cores can see it.
+
+When secondary cores boot up from 0xffff_f000 page, they only have one default
+TLB. While booting, they set up another TLB in AS=1 space and jump into
+the new space. The new TLB covers the physical address of the spin table page,
+with WIMGE =0b00100. Now secondary cores can keep polling the spin table
+without stress DDR bus because both the code and the spin table is in cache.
+
+For the above to work, DDR has to set the 'M' bit of WIMGE, in order to keep
+cache coherence.
diff --git a/doc/README.nokia_rx51 b/doc/README.nokia_rx51
new file mode 100644
index 0000000..a8fdfcd
--- /dev/null
+++ b/doc/README.nokia_rx51
@@ -0,0 +1,104 @@
+Board: Nokia RX-51 aka N900
+
+This board definition results in a u-boot.bin which can be chainloaded
+from NOLO in qemu or on a real N900. It does very little hardware config
+because NOLO has already configured the board. Only needed is enabling
+internal eMMC memory via twl4030 regulator which is not enabled by NOLO.
+
+NOLO is expecting a kernel image and will treat any image it finds in
+onenand as such. This u-boot is intended to be flashed to the N900 like
+a kernel. In order to transparently boot the original kernel, it will be
+appended to u-boot.bin at 0x40000. NOLO will load the entire image into
+(random) memory and execute u-boot, which saves hw revision, boot reason
+and boot mode ATAGs set by NOLO. Then the bootscripts will attempt to load
+uImage or boot.scr from a fat, ext2/ext3 or ext4 filesystem in external
+SD card or internal eMMC memory. If this fails or keyboard is closed then
+the appended kernel image will be booted using some generated and some
+stored ATAGs (see boot order).
+
+There is support for hardware watchdog. Hardware watchdog is started by
+NOLO so u-boot must kick watchdog to prevent reboot device (but not very
+often, max every 2 seconds). There is also support for framebuffer display
+output with ANSI espace codes and the N900 HW keyboard input. USB tty works
+but is disabled because it prevents the current Maemo kernel from booting.
+
+When U-Boot is starting it enable IBE bit in Auxiliary Control Register,
+which is needed for Thumb-2 ISA support. It is workaround for errata 430973.
+
+Default boot order:
+
+ * 0. if keyboard is closed boot automatically attached kernel image
+ * 1. try boot from external SD card
+ * 2. try boot from internal eMMC memory
+ * 3. try boot from attached kernel image
+
+Boot from SD or eMMC in this order:
+
+ * 1.
+   * 1.1 find boot.scr on first fat partition
+   * 1.2 find uImage on first fat parition
+   * 1.3 same order for 2. - 4. fat partition
+ * 2. same as 1. but for ext2/3 partition
+ * 3. same as 1. but for ext4 partition
+
+
+Available additional commands/variables:
+
+ * run sercon - Use serial port for control
+ * run usbcon - Use usbtty for control
+ * run vgacon - Use framebuffer and HW keyboard for control (default)
+
+ * run sdboot - Boot from external SD card (see boot order)
+ * run emmcboot - Boot from internal eMMC memory (see boot order)
+ * run attachboot - Boot attached kernel image (attached to U-Boot binary)
+
+ * run scriptload - Load boot script ${mmcscriptfile}
+ * run scriptboot - Run loaded boot script
+ * run kernload - Load kernel image ${mmckernfile}
+ * run initrdload - Load initrd image ${mmcinitrdfile}
+ * run kernboot - Boot loaded kernel image
+ * run kerninitrdboot - Boot loaded kernel image with loaded initrd image
+
+ * run trymmcscriptboot - Try to load and boot script ${mmcscriptfile}
+ * run trymmckernboot - Try to load and boot kernel image ${mmckernfile}
+ * run trymmckerninitrdboot - Try to load and boot kernel image ${mmckernfile}
+                              with initrd image ${mmcinitrdfile}
+
+Additional variables for loading files from mmc:
+
+ * mmc ${mmcnum} (0 - external, 1 - internal)
+ * partition number ${mmcpart} (1 - 4)
+ * parition type ${mmctype} (fat, ext2)
+
+Additional varuables for booting kernel:
+
+ * setup_omap_atag - Add OMAP table into atags structure (needs maemo kernel)
+ * setup_console_atag - Enable serial console in OMAP table
+ * setup_boot_reason_atag - Change boot reason in OMAP table
+ * setup_boot_mode_atag - Change boot mode in OMAP table
+
+USB TTY:
+
+ Maemo kernel 2.6.28 will crash if u-boot enable usb tty. So USB TTY is disabled.
+ For enabling USB TTY just add this line to file include/configs/nokia_rx51.h
+
+ #define CONFIG_USB_TTY
+
+
+ONENAND support:
+
+ ONENAND support is disabled because not working yet and cause linux kernel to
+ crash or no access to mtd. For enabling ONENAND support add this line at begin
+ of file include/configs/nokia_rx51.h
+
+ #define ONENAND_SUPPORT
+
+
+UBIFS support:
+
+ UBIFS support is disabled, because U-Boot image is too big and cannot be
+ flashed with attached zImage to RX-51 kernel nand area. For enabling UBIFS
+ support first enable ONENAND support and then add this line at begin of file
+ include/configs/nokia_rx51.h
+
+ #define UBIFS_SUPPORT
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index d0f4716..2b868e6 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -11,7 +11,14 @@ easily if here is something they might want to dig for...
 
 Board	Arch	CPU	removed	    Commit	last known maintainer/contact
 =============================================================================
-TQM85xx	powerpc	MPC85xx	-	  -		Stefan Roese <sr@denx.de>
+AMX860	powerpc	mpc860	-	  -		Wolfgang Denk <wd@denx.de>
+c2mon	powerpc	mpc855	-	  -		Wolfgang Denk <wd@denx.de>
+ETX094	powerpc	mpc850	-	  -		Wolfgang Denk <wd@denx.de>
+IAD210	powerpc	mpc860	-	  -		-
+LANTEC	powerpc	mpc850	-	  -		Wolfgang Denk <wd@denx.de>
+SCM	powerpc	mpc8260	-	  -		Wolfgang Grandegger <wg@denx.de>
+SX1	arm	arm925t	-         -
+TQM85xx	powerpc	MPC85xx	d923a5d5  2012-10-04	Stefan Roese <sr@denx.de>
 apollon arm     omap24xx 535c74f  2012-09-18    Kyungmin Park <kyungmin.park@samsung.com>
 tb0229	mips	mips32	3f3110d	  2011-12-12
 rmu	powerpc	MPC850	fb82fd7   2011-12-07	Wolfgang Denk <wd@denx.de>
diff --git a/doc/README.t4240qds b/doc/README.t4240qds
new file mode 100644
index 0000000..677d120
--- /dev/null
+++ b/doc/README.t4240qds
@@ -0,0 +1,98 @@
+Overview
+--------
+The T4240QDS is a high-performance computing evaluation, development and test
+platform supporting the T4240 QorIQ™ Power Architecture™ processor. T4240QDS is
+optimized to support the high-bandwidth DDR3 memory ports, as well as the
+highly-configurable SerDes ports. The system is lead-free and RoHS-compliant.
+
+Board Features
+  SERDES Connections
+	32 lanes grouped into four 8-lane banks
+	Two “front side” banks dedicated to Ethernet
+		- High-speed crosspoint switch fabric on selected lanes
+		- Two PCI Express slots with side-band connector supporting
+		- SGMII
+		- XAUI
+		- HiGig
+		- I-pass connectors allow board-to-board and loopback support
+	Two “back side” banks dedicated to other protocols
+		- High-speed crosspoint switch fabric on all lanes
+		- Four PCI Express slots with side-band connector supporting
+		- PCI Express 3.0
+		- SATA 2.0
+		- SRIO 2.0
+		- Supports 4X Aurora debug with two connectors
+  DDR Controllers
+	Three independant 64-bit DDR3 controllers
+	Supports rates of 1866 up to 2133 MHz data-rate
+	Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
+	DDR power supplies 1.5V to all devices with automatic tracking of VTT.
+	Power software-switchable to 1.35V if software detects all DDR3LP devices.
+	MT9JSF25672AZ-2G1KZESZF has been tested at 1333, 1600, 1867, 2000 and
+	2133MT/s speeds. For 1867MT/s and above, read-to-write turnaround time
+	increases by 1 clock.
+
+  IFC/Local Bus
+	NAND flash: 8-bit, async or sync, up to 2GB.
+	NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB
+	NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
+		- NOR devices support 16 virtual banks
+	GASIC: Minimal target within Qixis FPGA
+	PromJET rapid memory download support
+	Address demultiplexing handled within FPGA.
+		- Flexible demux allows 8 or 16 bit evaluation.
+	IFC Debug/Development card
+		- Support for 32-bit devices
+  Ethernet
+	Support two on-board RGMII 10/100/1G ethernet ports.
+	SGMII and XAUI support via SERDES block (see above).
+	1588 support via Symmetricom board.
+  QIXIS System Logic FPGA
+	Manages system power and reset sequencing
+	Manages DUT, board, clock, etc. configuration for dynamic shmoo
+	Collects V-I-T data in background for code/power profiling.
+	Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion)
+	General fault monitoring and logging
+	Runs from ATX “hot” power rails allowing operation while system is off.
+  Clocks
+	System and DDR clock (SYSCLK, “DDRCLK”)
+		- Switch selectable to one of 16 common settings in the interval 33MHz-166MHz.
+		- Software selectable in 1MHz increments from 1-200MHz.
+	SERDES clocks
+		- Provides clocks to all SerDes blocks and slots
+		- 100, 125 and 156.25 MHz
+  Power Supplies
+	Dedicated regulators for VDD
+		- Adjustable from (0.7V to 1.3V at 80A
+		- Regulators can be controlled by VID and/or software
+	Dedicated regulator for GVDD_PL: 1.35/1.5V at 22A
+		- VTT/MVREF automatically track operating voltage
+	Dedicated regulators/filters for AVDD supplies
+	Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, POVDD, etc.
+  USB
+	Supports two USB 2.0 ports with integrated PHYs
+		- One type A, one type micro-AB with 1.0A power per port.
+  Other IO
+	eSDHC/MMC
+		- SDHC card slot
+	eSPI port
+		- High-speed serial flash
+	Two Serial port
+	Four I2C ports
+
+Memory map
+----------
+The addresses in brackets are physical addresses.
+
+0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff   2GB DDR (more than 2GB is initialized but not mapped under with TLB)
+0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory
+0x0_f000_0000 (0xf_0000_0000) - 0x0_f03f_ffff  4MB  DCSR
+0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff  32MB BMan
+0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff  32MB QMan
+0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO
+0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash
+0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff  16MB CCSR
+0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff   4KB QIXIS
+0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff   4KB Boot page translation for secondary cores
+
+The physical address of the last (boot page translation) varies with the actual DDR size.
diff --git a/doc/driver-model/UDM-serial.txt b/doc/driver-model/UDM-serial.txt
index e9c274d..c6a8ab0 100644
--- a/doc/driver-model/UDM-serial.txt
+++ b/doc/driver-model/UDM-serial.txt
@@ -125,67 +125,59 @@ III) Analysis of in-tree drivers
   -------------------
   No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
 
-  17) serial_lh7a40x.c
+  17) serial_max3100.c
   --------------------
   No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
 
-  18) serial_lpc2292.c
-  --------------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  19) serial_max3100.c
-  --------------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  20) serial_mxc.c
+  18) serial_mxc.c
   ----------------
   No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
 
-  21) serial_netarm.c
+  19) serial_netarm.c
   -------------------
   No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
 
-  22) serial_pl01x.c
+  20) serial_pl01x.c
   ------------------
   No support for CONFIG_SERIAL_MULTI. Simple conversion possible, though this
   driver in fact contains two drivers in total.
 
-  23) serial_pxa.c
+  21) serial_pxa.c
   ----------------
   This driver is a bit complicated, but due to clean support for
   CONFIG_SERIAL_MULTI, there are no expected obstructions throughout the
   conversion process.
 
-  24) serial_s3c24x0.c
+  22) serial_s3c24x0.c
   --------------------
   This driver, being quite ad-hoc might need some work to bring back to shape.
 
-  25) serial_s3c44b0.c
+  23) serial_s3c44b0.c
   --------------------
   No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
 
-  26) serial_s5p.c
+  24) serial_s5p.c
   ----------------
   No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
 
-  27) serial_sa1100.c
+  25) serial_sa1100.c
   -------------------
   No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
 
-  28) serial_sh.c
+  26) serial_sh.c
   ---------------
   No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
 
-  29) serial_xuartlite.c
+  27) serial_xuartlite.c
   ----------------------
   No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
 
-  30) usbtty.c
+  28) usbtty.c
   ------------
   This driver seems very complicated and entangled with USB framework. The
   conversion might be complicated here.
 
-  31) arch/powerpc/cpu/mpc512x/serial.c
+  29) arch/powerpc/cpu/mpc512x/serial.c
   -------------------------------------
   This driver supports CONFIG_SERIAL_MULTI. This driver will need to be moved to
   proper place.
diff --git a/doc/git-mailrc b/doc/git-mailrc
index 7f60ef1..6600c15 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -30,6 +30,7 @@ alias rbohmer        Remy Bohmer <linux@bohmer.net>
 alias reinhardm      Reinhard Meyer <u-boot@emk-elektronik.de>
 alias sbabic         Stefano Babic <sbabic@denx.de>
 alias scottwood      Scott Wood <scottwood@freescale.com>
+alias sjg            Simon Glass <sjg@chromium.org>
 alias smcnutt        Scott McNutt <smcnutt@psyent.com>
 alias stroese        Stefan Roese <sr@denx.de>
 alias vapier         Mike Frysinger <vapier@gentoo.org>
@@ -50,7 +51,7 @@ alias rmobile        uboot, iwamatsu
 alias s3c            samsung
 alias s5pc           samsung
 alias samsung        uboot, prom
-alias tegra          uboot, Simon Glass <sjg@chromium.org>, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com>
+alias tegra          uboot, sjg, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com>
 alias tegra2         tegra
 alias ti             uboot, Tom Rini <trini@ti.com>
 
@@ -84,7 +85,7 @@ alias ppc4xx         uboot, stroese
 alias ppc7xx         uboot, wd
 alias ppc74xx        uboot, wd
 
-alias sandbox        Simon Glass <sjg@chromium.org>
+alias sandbox        sjg
 alias sb             sandbox
 
 alias sparc          uboot, Daniel Hellstrom <daniel@gaisler.com>
@@ -92,7 +93,7 @@ alias sparc          uboot, Daniel Hellstrom <daniel@gaisler.com>
 alias superh         uboot, iwamatsu
 alias sh             superh
 
-alias x86            uboot, gruss
+alias x86            uboot, sjg, gruss
 
 # Subsystem aliases
 alias cfi            uboot, stroese