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authorPaul Gortmaker <paul.gortmaker@windriver.com>2011-12-30 23:53:12 -0500
committerKumar Gala <galak@kernel.crashing.org>2012-01-11 13:59:14 -0600
commit3e3262bd149e21d0f5a82648218c26f2aa0e15e7 (patch)
tree954100513b29dbcea5804303864c74d75ba729b0 /doc
parent2a6b3b74d85cff3f9a76edd09a7b2e8e25bb4eb4 (diff)
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sbc8548: enable support for hardware SPD errata workaround
Existing boards by default have an issue where the LBC SDRAM SPD EEPROM and the DDR2 SDRAM SPD EEPROM both land at 0x51. After the hardware modification listed in the README is made, then the DDR2 SPD EEPROM appears at 0x53. So this implements a board specific get_spd() by taking advantage of the existing weak linkage, that 1st tries reading at 0x53 and then if that fails, it falls back to the old 0x51. Since the old dependency issue of "SPD implies no LBC SDRAM" gets removed with the hardware errata fix, remove that restriction in the code, so both LBC SDRAM and SPD can be selected. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'doc')
-rw-r--r--doc/README.sbc854820
1 files changed, 18 insertions, 2 deletions
diff --git a/doc/README.sbc8548 b/doc/README.sbc8548
index f9e2dea..0f3f543 100644
--- a/doc/README.sbc8548
+++ b/doc/README.sbc8548
@@ -71,7 +71,22 @@ EEPROM data to read what memory is installed.
There is a hardware errata, which causes the older local bus SDRAM
SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so
-that the SPD data can not be read reliably.
+that the SPD data can not be read reliably. You can test if your
+board has the errata fix by running "i2c probe". If you see 0x53
+as a valid device, it has been fixed. If you only see 0x50, 0x51
+then your board does not have the fix.
+
+You can also visually inspect the board to see if this hardware
+fix has been applied:
+
+ 1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on
+ the back of the PCB behind the DDR SDRAM SODIMM connector.
+ 2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad
+ to R313 pin 2. Pin 2 for each resistor is the end of the
+ resistor closest to the CPU.
+
+Boards without the mod will have R314 and R313 in parallel, like "||".
+After the mod, they will be touching and form an "L" shape.
If you want to upgrade to larger RAM size, you can simply enable
#define CONFIG_SPD_EEPROM
@@ -79,7 +94,8 @@ If you want to upgrade to larger RAM size, you can simply enable
in include/configs/sbc8548.h file. (The lines are already there
but listed as #undef).
-Note that you will have to physically remove the LBC 128MB DIMM
+If you did the i2c test, and your board does not have the errata
+fix, then you will have to physically remove the LBC 128MB DIMM
from the board's socket to resolve the above i2c address overlap
issue and allow SPD autodetection of RAM to work.