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| author | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:59:44 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:59:44 +0200 |
| commit | f82642e33899766892499b163e60560fbbf87773 (patch) | |
| tree | ab90f076f18e56b2b3e8c9375b95917daa78c1d9 /doc | |
| parent | b59b16ca24bc7e77ec113021a6d77b9b32fcf192 (diff) | |
| parent | 360fe71e82b83e264c964c9447c537e9a1f643c8 (diff) | |
| download | u-boot-imx-f82642e33899766892499b163e60560fbbf87773.zip u-boot-imx-f82642e33899766892499b163e60560fbbf87773.tar.gz u-boot-imx-f82642e33899766892499b163e60560fbbf87773.tar.bz2 | |
Merge 'next' branch
Conflicts:
board/freescale/mpc8536ds/mpc8536ds.c
include/configs/mgcoge.h
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'doc')
42 files changed, 793 insertions, 712 deletions
diff --git a/doc/I2C_Edge_Conditions b/doc/I2C_Edge_Conditions index 44d3478..f4a9968 100644 --- a/doc/I2C_Edge_Conditions +++ b/doc/I2C_Edge_Conditions @@ -33,7 +33,7 @@ Notes This reset edge condition could possibly be present in every I2C controller and device available. For boards where a I2C bus reset function can be implemented a i2c_init_board() function should be -provided and enabled by #define'ing CFG_I2C_INIT_BOARD in your +provided and enabled by #define'ing CONFIG_SYS_I2C_INIT_BOARD in your board's config file. Note that this is NOT necessary when using the bit-banging I2C driver (common/soft_i2c.c) as this already includes the I2C bus reset sequence. diff --git a/doc/README.JFFS2 b/doc/README.JFFS2 index c5d67fd..f0e9bc1 100644 --- a/doc/README.JFFS2 +++ b/doc/README.JFFS2 @@ -12,7 +12,7 @@ chpart - change active partition If you boot from a partition which is mounted writable, and you update your boot environment by replacing single files on that -partition, you should also define CFG_JFFS2_SORT_FRAGMENTS. Scanning +partition, you should also define CONFIG_SYS_JFFS2_SORT_FRAGMENTS. Scanning the JFFS2 filesystem takes *much* longer with this feature, though. Sorting is done while inserting into the fragment list, which is more or less a bubble sort. That algorithm is known to be O(n^2), @@ -24,16 +24,16 @@ the flash_info structure to find the start of a JFFS2 disk (called partition in the code) and you can change where the partition is with two defines. -CFG_JFFS2_FIRST_BANK +CONFIG_SYS_JFFS2_FIRST_BANK defined the first flash bank to use -CFG_JFFS2_FIRST_SECTOR +CONFIG_SYS_JFFS2_FIRST_SECTOR defines the first sector to use -The second way is to define CFG_JFFS_CUSTOM_PART and implement the +The second way is to define CONFIG_SYS_JFFS_CUSTOM_PART and implement the jffs2_part_info(int part_num) function in your board specific files. -In this mode CFG_JFFS2_FIRST_BANK and CFG_JFFS2_FIRST_SECTOR is not +In this mode CONFIG_SYS_JFFS2_FIRST_BANK and CONFIG_SYS_JFFS2_FIRST_SECTOR is not used. The input is a partition number starting with 0. @@ -41,7 +41,7 @@ Return a pointer to struct part_info or NULL for error; Ex jffs2_part_info() for one partition. --- -#if defined CFG_JFFS_CUSTOM_PART +#if defined CONFIG_SYS_JFFS_CUSTOM_PART #include <jffs2/jffs2.h> static struct part_info part; diff --git a/doc/README.JFFS2_NAND b/doc/README.JFFS2_NAND index a836d53..2b3326b 100644 --- a/doc/README.JFFS2_NAND +++ b/doc/README.JFFS2_NAND @@ -13,7 +13,7 @@ configured using the following #defines in the configuration file: #define CONFIG_JFFS2_NAND_SIZE 2*1024*1024 /* size of jffs2 partition */ If more than a single partition is desired, the user can define a -CFG_JFFS_CUSTOM_PART macro and implement a +CONFIG_SYS_JFFS_CUSTOM_PART macro and implement a struct part_info* jffs2_part_info(int part_num) diff --git a/doc/README.MBX b/doc/README.MBX index 679228e..c889fe9 100644 --- a/doc/README.MBX +++ b/doc/README.MBX @@ -1,4 +1,4 @@ -IMPORTANT NOTE - read before defining CFG_USE_OSCCLK in your board +IMPORTANT NOTE - read before defining CONFIG_SYS_USE_OSCCLK in your board config file!!! @@ -62,7 +62,7 @@ firmware opts for the NASTY timing loops, but needs to configure the serial ports to do so. -You may have a legitimate need to define CFG_USE_OSCCLK if your +You may have a legitimate need to define CONFIG_SYS_USE_OSCCLK if your MBX8xx board is using the OSCM clocking mode. You better know what you are doing here. diff --git a/doc/README.MPC866 b/doc/README.MPC866 index c8256a1..4707cb7 100644 --- a/doc/README.MPC866 +++ b/doc/README.MPC866 @@ -4,8 +4,8 @@ clock value, in MHz, via an environment variable "cpuclk". Four compile-time constants are used: CONFIG_8xx_OSCLK - input quartz clock - CFG_8xx_CPUCLK_MIN - minimum allowed CPU clock - CFG_8xx_CPUCLK_MAX - maximum allowed CPU clock + CONFIG_SYS_8xx_CPUCLK_MIN - minimum allowed CPU clock + CONFIG_SYS_8xx_CPUCLK_MAX - maximum allowed CPU clock CONFIG_8xx_CPUCLK_DEFAULT - default CPU clock value If the "cpuclk" environment variable value is within the CPUCLK_MIN / diff --git a/doc/README.PIP405 b/doc/README.PIP405 index 07756a5..d8b3f9c 100644 --- a/doc/README.PIP405 +++ b/doc/README.PIP405 @@ -100,9 +100,9 @@ CONFIG_ATAPI enables ATAPI Support SCSI support (experimental) only SYM53C8xx supported ---------------------------------------------------- CONFIG_SCSI_SYM53C8XX type of SCSI controller -CFG_SCSI_MAX_LUN 8 number of supported LUNs -CFG_SCSI_MAX_SCSI_ID 7 maximum SCSI ID (0..6) -CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN +CONFIG_SYS_SCSI_MAX_LUN 8 number of supported LUNs +CONFIG_SYS_SCSI_MAX_SCSI_ID 7 maximum SCSI ID (0..6) +CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN maximum of Target devices (multiple LUN support for boot) @@ -125,7 +125,7 @@ CONFIG_VIDEO_CT69000 Enable Chips & Technologies 69000 Video chip External peripheral base address: --------------------------------- -CFG_ISA_IO_BASE_ADDRESS address of all ISA-bus related parts +CONFIG_SYS_ISA_IO_BASE_ADDRESS address of all ISA-bus related parts _must_ be defined for ISA-bus parts Identify: @@ -135,14 +135,14 @@ CONFIG_IDENT_STRING added to the U_BOOT_VERSION String Environment / Console: ---------------------- -CFG_CONSOLE_IS_IN_ENV if defined, stdin, stdout and stderr used from +CONFIG_SYS_CONSOLE_IS_IN_ENV if defined, stdin, stdout and stderr used from the values stored in the evironment. -CFG_CONSOLE_OVERWRITE_ROUTINE if defined, console_overwrite() decides if the +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE if defined, console_overwrite() decides if the values stored in the environment or the standard serial in/out put should be assigned to the console. -CFG_CONSOLE_ENV_OVERWRITE if defined, the start-up console switching +CONFIG_SYS_CONSOLE_ENV_OVERWRITE if defined, the start-up console switching are stored in the environment. PIP405 specific: @@ -161,7 +161,7 @@ Added Devices: Floppy support: --------------- -Support of a standard floppy disk controller at address CFG_ISA_IO_BASE_ADDRESS +Support of a standard floppy disk controller at address CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x3F0. Enabled with define CONFIG_CMD_FDC. Reads a unformated floppy disk with a image header (see: mkimage). No interrupts and no DMA are used for this. Added files: @@ -173,7 +173,7 @@ SCSI support: Support for Symbios SYM53C810A chip. Implemented as follows: - without disconnect - only asynchrounous -- multiple LUN support (caution, needs a lot of RAM. define CFG_SCSI_MAX_LUN 1 to +- multiple LUN support (caution, needs a lot of RAM. define CONFIG_SYS_SCSI_MAX_LUN 1 to save RAM) - multiple SCSI ID support - no write support @@ -197,7 +197,7 @@ ATAPI support (IDE changes): ---------------------------- Added ATAPI support (with CONFIG_ATAPI) in the file cmd_ide.c. To support a hardreset, when the IDE reset pin is not connected to the -CFG_PC_IDE_RESET pin, the switch CONFIG_IDE_RESET_ROUTINE has been added. When +CONFIG_SYS_PC_IDE_RESET pin, the switch CONFIG_IDE_RESET_ROUTINE has been added. When this switch is enabled the routine void ide_set_reset(int idereset) must be within the board specific files. Only read from ATAPI devices are supported. @@ -242,7 +242,7 @@ changed files: MC146818 RTC support: --------------------- Added support for MC146818 RTC with defining CONFIG_RTC_MC146818. The ISA bus IO -base address must be defined with CFG_ISA_IO_BASE_ADDRESS. +base address must be defined with CONFIG_SYS_ISA_IO_BASE_ADDRESS. Added files: - rtc/mc146818.c @@ -299,7 +299,7 @@ I2C Stuff: ---------- Added defined(CONFIG_PIP405) at several points in common/cmd_i2c.c. Added 16bit read/write support for I2C (PPC405), and page write to -I2C EEPROM if defined CFG_EEPROM_PAGE_WRITE_ENABLE. +I2C EEPROM if defined CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE. Changed files: - cpu/ppc4xx/i2c.c - common/cmd_i2c.c @@ -308,11 +308,11 @@ Environment / Console: ---------------------- Although in README.console described, the U-Boot has not assinged the values found in the environment to the console. Corrected this behavior, but only if -CFG_CONSOLE_IS_IN_ENV is defined. -If CFG_CONSOLE_OVERWRITE_ROUTINE is defined, console_overwrite() decides if the +CONFIG_SYS_CONSOLE_IS_IN_ENV is defined. +If CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is defined, console_overwrite() decides if the values stored in the environment or the standard serial in/output should be assigned to the console. This is useful if the environment values are not correct. -If CFG_CONSOLE_ENV_OVERWRITE is defined the devices assigned to the console at +If CONFIG_SYS_CONSOLE_ENV_OVERWRITE is defined the devices assigned to the console at start-up time will be written to the environment. This means that if the environment values are overwritten by the overwrite_console() routine, they will be stored in the environment. diff --git a/doc/README.PXA_CF b/doc/README.PXA_CF index e443d39..6a0f236 100644 --- a/doc/README.PXA_CF +++ b/doc/README.PXA_CF @@ -12,35 +12,35 @@ are imposed by the PXA architecture. #define CONFIG_PCMCIA_SLOT_A 1 /* just to keep build system happy */ -#define CFG_PCMCIA_MEM_ADDR 0x28000000 -#define CFG_PCMCIA_MEM_SIZE 0x10000000 - -#define CFG_MECR_VAL 0x00000000 -#define CFG_MCMEM0_VAL 0x00004204 -#define CFG_MCMEM1_VAL 0x00000000 -#define CFG_MCATT0_VAL 0x00010504 -#define CFG_MCATT1_VAL 0x00000000 -#define CFG_MCIO0_VAL 0x00008407 -#define CFG_MCIO1_VAL 0x00000000 +#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x28000000 +#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x10000000 + +#define CONFIG_SYS_MECR_VAL 0x00000000 +#define CONFIG_SYS_MCMEM0_VAL 0x00004204 +#define CONFIG_SYS_MCMEM1_VAL 0x00000000 +#define CONFIG_SYS_MCATT0_VAL 0x00010504 +#define CONFIG_SYS_MCATT1_VAL 0x00000000 +#define CONFIG_SYS_MCIO0_VAL 0x00008407 +#define CONFIG_SYS_MCIO1_VAL 0x00000000 /* memory configuration */ -#define CFG_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ -#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_BASE_ADDR 0x20000000 +#define CONFIG_SYS_ATA_BASE_ADDR 0x20000000 /* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET 0x1f0 +#define CONFIG_SYS_ATA_DATA_OFFSET 0x1f0 /* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET 0x1f0 +#define CONFIG_SYS_ATA_REG_OFFSET 0x1f0 /* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x3f0 +#define CONFIG_SYS_ATA_ALT_OFFSET 0x3f0 Another important point is that maybe you have to power the pcmcia diff --git a/doc/README.TQM8260 b/doc/README.TQM8260 index 0571095..b93a1cb 100644 --- a/doc/README.TQM8260 +++ b/doc/README.TQM8260 @@ -52,7 +52,7 @@ CONFIG_82xx_CONS_SMC2 If defined, SMC2 will be used as the console -CFG_INIT_LOCAL_SDRAM +CONFIG_SYS_INIT_LOCAL_SDRAM If defined, the SDRAM on the local bus will be initialized and mapped at BR2. diff --git a/doc/README.adnpesc1 b/doc/README.adnpesc1 index 5257f18..f9566b8 100644 --- a/doc/README.adnpesc1 +++ b/doc/README.adnpesc1 @@ -78,7 +78,7 @@ configuration settings occupies about 97 KBytes of flash. A minimal configuration occupies less than 70 KByte (network, SPI, POST and board command support disabled). You can save more memory by deactivating the Hu-Shell support and -long command help (CFG_HUSH_PARSER, CFG_LONGHELP). +long command help (CONFIG_SYS_HUSH_PARSER, CONFIG_SYS_LONGHELP). To program U-Boot into the ADNP/ESC1 flash using GERMS do the following: @@ -193,24 +193,24 @@ you have to check-up the next environment variables: - this is the startup address for autoboot - each Nios application code we want to update will be copied to this address - - default is CFG_ADNPESC1_NIOS_APPL_ENTRY + - default is CONFIG_SYS_ADNPESC1_NIOS_APPL_ENTRY 3. appl_end_addr - Nios application area end address (usually in Flash) - will be used to unprotect/erase the Flash area while updating - - default is CFG_ADNPESC1_NIOS_APPL_END + - default is CONFIG_SYS_ADNPESC1_NIOS_APPL_END 4. appl_ident_addr - address of the Nios application identification string - this is the address checked-up by autoboot - - default is CFG_ADNPESC1_NIOS_APPL_IDENT + - default is CONFIG_SYS_ADNPESC1_NIOS_APPL_IDENT 5. appl_ident_str - the Nios application identification string itself - - default is CFG_ADNPESC1_NIOS_IDENTIFIER + - default is CONFIG_SYS_ADNPESC1_NIOS_IDENTIFIER 6. appl_name @@ -221,13 +221,13 @@ you have to check-up the next environment variables: - optionally file system area start address (usually in Flash) - each file system we want to update will be copied to this address - - default is CFG_ADNPESC1_FILESYSTEM_BASE + - default is CONFIG_SYS_ADNPESC1_FILESYSTEM_BASE 8. fs_end_addr - optionally file system area end address (usually in Flash) - will be used to unprotect/erase the Flash area while updating - - default is CFG_ADNPESC1_FILESYSTEM_END + - default is CONFIG_SYS_ADNPESC1_FILESYSTEM_END 9. fs_name diff --git a/doc/README.adnpesc1_base32 b/doc/README.adnpesc1_base32 index 145e8cd..e6fb7a4 100644 --- a/doc/README.adnpesc1_base32 +++ b/doc/README.adnpesc1_base32 @@ -18,39 +18,39 @@ CPU: "DNP_ESC1" no Debug Core no On Chip Instrumentation (OCI) - U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000 - CFG_NIOS_CPU_ICACHE = (not present) - CFG_NIOS_CPU_DCACHE = (not present) - CFG_NIOS_CPU_REG_NUMS = 512 - CFG_NIOS_CPU_MUL = 0 - CFG_NIOS_CPU_MSTEP = 1 - CFG_NIOS_CPU_DBG_CORE = 0 + U-Boot CFG: CONFIG_SYS_NIOS_CPU_CLK = 50000000 + CONFIG_SYS_NIOS_CPU_ICACHE = (not present) + CONFIG_SYS_NIOS_CPU_DCACHE = (not present) + CONFIG_SYS_NIOS_CPU_REG_NUMS = 512 + CONFIG_SYS_NIOS_CPU_MUL = 0 + CONFIG_SYS_NIOS_CPU_MSTEP = 1 + CONFIG_SYS_NIOS_CPU_DBG_CORE = 0 IRQ: Nr. | used by ------+-------------------------------------------------------- - 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16 - 17 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 17 - 18 | UART1 | CFG_NIOS_CPU_UART1_IRQ = 18 - 20 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = - | PIO6 | CFG_NIOS_CPU_PIO6_IRQ = 20 - 25 | SPI0 | CFG_NIOS_CPU_SPI0_IRQ = 25 - 31 | PIO7 | CFG_NIOS_CPU_PIO7_IRQ = 31 - 32 | PIO8 | CFG_NIOS_CPU_PIO8_IRQ = 32 - 33 | PIO9 | CFG_NIOS_CPU_PIO9_IRQ = 33 - 34 | PIO10 | CFG_NIOS_CPU_PIO10_IRQ = 34 - 35 | PIO11 | CFG_NIOS_CPU_PIO11_IRQ = 35 - 36 | PIO12 | CFG_NIOS_CPU_PIO12_IRQ = - | IDE0 | CFG_NIOS_CPU_IDE0_IRQ = 36 - 37 | PIO13 | CFG_NIOS_CPU_PIO13_IRQ = - | IDE1 | CFG_NIOS_CPU_IDE1_IRQ = 37 + 16 | TIMER0 | CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 16 + 17 | UART0 | CONFIG_SYS_NIOS_CPU_UART0_IRQ = 17 + 18 | UART1 | CONFIG_SYS_NIOS_CPU_UART1_IRQ = 18 + 20 | LAN91C111 | CONFIG_SYS_NIOS_CPU_LAN0_IRQ = + | PIO6 | CONFIG_SYS_NIOS_CPU_PIO6_IRQ = 20 + 25 | SPI0 | CONFIG_SYS_NIOS_CPU_SPI0_IRQ = 25 + 31 | PIO7 | CONFIG_SYS_NIOS_CPU_PIO7_IRQ = 31 + 32 | PIO8 | CONFIG_SYS_NIOS_CPU_PIO8_IRQ = 32 + 33 | PIO9 | CONFIG_SYS_NIOS_CPU_PIO9_IRQ = 33 + 34 | PIO10 | CONFIG_SYS_NIOS_CPU_PIO10_IRQ = 34 + 35 | PIO11 | CONFIG_SYS_NIOS_CPU_PIO11_IRQ = 35 + 36 | PIO12 | CONFIG_SYS_NIOS_CPU_PIO12_IRQ = + | IDE0 | CONFIG_SYS_NIOS_CPU_IDE0_IRQ = 36 + 37 | PIO13 | CONFIG_SYS_NIOS_CPU_PIO13_IRQ = + | IDE1 | CONFIG_SYS_NIOS_CPU_IDE1_IRQ = 37 MEMORY: 8 MByte Flash 16 MByte SDRAM Timer: TIMER0: high priority programmable timer (IRQ16) - U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 0 - CFG_NIOS_CPU_USER_TIMER = (not present) + U-Boot CFG: CONFIG_SYS_NIOS_CPU_TICK_TIMER = 0 + CONFIG_SYS_NIOS_CPU_USER_TIMER = (not present) PIO: Nr. | description ------+-------------------------------------------------------- @@ -71,13 +71,13 @@ PIO: Nr. | description PIO13| INT7: 1 input for general purpose irq (IRQ37) | IDE1INT: (same) for IDE1 irq input - U-Boot CFG: CFG_NIOS_CPU_PORTA_PIO = 0 - CFG_NIOS_CPU_PORTB_PIO = 1 - CFG_NIOS_CPU_PORTC_PIO = 2 - CFG_NIOS_CPU_RCM_PIO = 3 - CFG_NIOS_CPU_WDTENA_PIO = 4 - CFG_NIOS_CPU_WDTTRIG_PIO = 5 - CFG_NIOS_CPU_LED_PIO = (not present) + U-Boot CFG: CONFIG_SYS_NIOS_CPU_PORTA_PIO = 0 + CONFIG_SYS_NIOS_CPU_PORTB_PIO = 1 + CONFIG_SYS_NIOS_CPU_PORTC_PIO = 2 + CONFIG_SYS_NIOS_CPU_RCM_PIO = 3 + CONFIG_SYS_NIOS_CPU_WDTENA_PIO = 4 + CONFIG_SYS_NIOS_CPU_WDTTRIG_PIO = 5 + CONFIG_SYS_NIOS_CPU_LED_PIO = (not present) UART: UART0: fixed baudrate of 115200, fixed protocol 8N1, RTS/CTS (IRQ17) UART1: fixed baudrate of 115200, fixed protocol 8N1, @@ -104,28 +104,28 @@ IDE: (TODO) 0x44000000 ---32-----------16|15------------0- | | | \ : (real size : : | - EXT3 (CS4) : and content : : > CFG_NIOS_CPU_CS3_SIZE + EXT3 (CS4) : and content : : > CONFIG_SYS_NIOS_CPU_CS3_SIZE : unknown) : : | = 0x01000000 | | | / - 0x43000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS3_BASE + 0x43000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_CS3_BASE | | | \ : (real size : : | - EXT2 (CS3) : and content : : > CFG_NIOS_CPU_CS2_SIZE + EXT2 (CS3) : and content : : > CONFIG_SYS_NIOS_CPU_CS2_SIZE : unknown) : : | = 0x01000000 | | | / - 0x42000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS2_BASE + 0x42000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_CS2_BASE | | | \ : (real size : : | - EXT1 (CS2) : and content : : > CFG_NIOS_CPU_CS1_SIZE + EXT1 (CS2) : and content : : > CONFIG_SYS_NIOS_CPU_CS1_SIZE : unknown) : : | = 0x01000000 | | | / - 0x41000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS1_BASE + 0x41000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_CS1_BASE | | | \ : (real size : : | - EXT0 (CS1) : and content : : > CFG_NIOS_CPU_CS0_SIZE + EXT0 (CS1) : and content : : > CONFIG_SYS_NIOS_CPU_CS0_SIZE : unknown) : : | = 0x01000000 | | | / - 0x40000000 ---32-----------16|15------------0- CFG_NIOS_CPU_CS0_BASE + 0x40000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_CS0_BASE | | : gap : : : @@ -135,23 +135,23 @@ IDE: (TODO) : : : gap : | | - 0x03000000 ---32-----------16|15------------0- CFG_NIOS_CPU_STACK + 0x03000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_STACK | . | \ | . | | (U-Boot run-time system) | . | | - | . | > CFG_MONITOR_LEN + | . | > CONFIG_SYS_MONITOR_LEN | . | | = 0x00040000 | . | | | . | / 0x02fc0000 --+32-----------16|15------------0+ TEXT_BASE | . | \ - | . | > CFG_MALLOC_LEN (heap) + | . | > CONFIG_SYS_MALLOC_LEN (heap) | . | / --+32-----------16|15------------0+ | . | \ - | . | > CFG_GBL_DATA_SIZE (global) + | . | > CONFIG_SYS_GBL_DATA_SIZE (global) | . | / - --+32-----------16|15------------0+ CFG_INIT_SP (u-boot stack) + --+32-----------16|15------------0+ CONFIG_SYS_INIT_SP (u-boot stack) | . | \ \ | . | | | | . | | > stack area @@ -159,17 +159,17 @@ IDE: (TODO) | . | | V | . | | | . | | - SDRAM | . | > CFG_NIOS_CPU_SDRAM_SIZE + SDRAM | . | > CONFIG_SYS_NIOS_CPU_SDRAM_SIZE | . | | = 0x01000000 | . | | 0x02000100 |- - - - - - - - - - - - - - - -+-|- | . | | \ | . | | | - | . | | > CFG_NIOS_CPU_VEC_SIZE + | . | | > CONFIG_SYS_NIOS_CPU_VEC_SIZE | . | | | = 0x00000100 | | / / - 0x02000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_VEC_BASE - 0x02000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SDRAM_BASE + 0x02000000 |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_VEC_BASE + 0x02000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_SDRAM_BASE | | \ : gap : > (space for 2nd Flash) | | / @@ -177,11 +177,11 @@ IDE: (TODO) | sector 127 | \ + 0x7f0000 |- - - - - - - - - - - - - - - -| | | : | | - Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE + Flash |- - - - : - - - -| > CONFIG_SYS_NIOS_CPU_FLASH_SIZE | sector 1 : | | = 0x00800000 + 0x010000 |- - - - - - - - - - - - - - - -| | | sector 0 (size = 0x10000) | / - 0x01000000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE + 0x01000000 ---8-------------4|3-------------0- CONFIG_SYS_NIOS_CPU_FLASH_BASE | | : gap : : : @@ -207,7 +207,7 @@ IDE: (TODO) | |- - - - - - -|- - - - - - -| | | | | EPH STATUS | TCR | | | | +---------------------------+ | / - 0x00010000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE + 0x00010000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_LAN0_BASE | | : gap : : : @@ -223,13 +223,13 @@ IDE: (TODO) IDE1 i/f : : : > 0x00000020 [5] : : : | | | | / - 0x00001020 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE1 + 0x00001020 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_IDE1 | | | \ : : : | IDE0 i/f : : : > 0x00000020 [5] : : : | | | | / - 0x00001000 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0 + 0x00001000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_IDE0 | | : gap : | | @@ -241,7 +241,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (ro) | / - 0x00000970 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO13 + 0x00000970 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO13 | edgecapture (1 bit) (rw) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO12 | interruptmask (1 bit) (rw) | | @@ -249,7 +249,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (ro) | / - 0x00000960 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO12 + 0x00000960 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO12 | edgecapture (1 bit) (rw) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO11 | interruptmask (1 bit) (rw) | | @@ -257,7 +257,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (ro) | / - 0x00000950 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO11 + 0x00000950 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO11 | edgecapture (1 bit) (rw) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO10 | interruptmask (1 bit) (rw) | | @@ -265,7 +265,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (ro) | / - 0x00000940 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO10 + 0x00000940 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO10 | edgecapture (1 bit) (rw) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO9 | interruptmask (1 bit) (rw) | | @@ -273,7 +273,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (ro) | / - 0x00000930 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO9 + 0x00000930 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO9 | edgecapture (1 bit) (rw) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO8 | interruptmask (1 bit) (rw) | | @@ -281,7 +281,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (ro) | / - 0x00000920 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO8 + 0x00000920 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO8 | edgecapture (1 bit) (rw) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO7 | interruptmask (1 bit) (rw) | | @@ -289,7 +289,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (ro) | / - 0x00000910 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO7 + 0x00000910 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO7 | edgecapture (1 bit) (rw) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO6 | interruptmask (1 bit) (rw) | | @@ -297,7 +297,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (ro) | / - 0x00000900 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO6 + 0x00000900 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO6 | | : gap : | | @@ -317,7 +317,7 @@ IDE: (TODO) | txdata (16 bit) (wo) | | + 0x04 |- - - - - - - - - - - - - - - -| | | rxdata (16 bit) (ro) | / - 0x000008c0 ---32-----------16|15------------0- CFG_NIOS_CPU_SPI0 + 0x000008c0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_SPI0 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO5 | (unused) | | @@ -325,7 +325,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (wo) | / - 0x000008b0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO5 + 0x000008b0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO5 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO4 | (unused) | | @@ -333,7 +333,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (wo) | / - 0x000008a0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO4 + 0x000008a0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO4 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO3 | (unused) | | @@ -341,7 +341,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (ro) | / - 0x00000890 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3 + 0x00000890 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO3 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO2 | (unused) | | @@ -349,7 +349,7 @@ IDE: (TODO) | direction (4 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (4 bit) (rw) | / - 0x00000880 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2 + 0x00000880 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO2 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO1 | (unused) | | @@ -357,7 +357,7 @@ IDE: (TODO) | direction (8 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (8 bit) (rw) | / - 0x00000870 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1 + 0x00000870 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO1 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO0 | (unused) | | @@ -365,7 +365,7 @@ IDE: (TODO) | direction (8 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (8 bit) (rw) | / - 0x00000860 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0 + 0x00000860 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO0 | (unused) | \ + 0x1c |- - - - - - - - - - - - - - - -| | | (unused) | | @@ -381,7 +381,7 @@ IDE: (TODO) | control (4 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | status (2 bit) (rw) | / - 0x00000840 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0 + 0x00000840 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_TIMER0 | (unused) | \ + 0x1c |- - - - - - - - - - - - - - - -| | | (unused) | | @@ -397,7 +397,7 @@ IDE: (TODO) | txdata (8 bit) (wo) | | + 0x04 |- - - - - - - - - - - - - - - -| | | rxdata (8 bit) (ro) | / - 0x00000820 ---32-----------16|15------------0- CFG_NIOS_CPU_UART1 + 0x00000820 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_UART1 | (unused) | \ + 0x1c |- - - - - - - - - - - - - - - -| | | (unused) | | @@ -413,18 +413,18 @@ IDE: (TODO) | txdata (8 bit) (wo) | | + 0x04 |- - - - - - - - - - - - - - - -| | | rxdata (8 bit) (ro) | / - 0x00000800 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0 + 0x00000800 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_UART0 - - - - - - - - - - - on chip memory 1 - - - - - - - - - - - 0x00000800 ---32-----------16|15------------0- | : | \ | : | | - GERMS | : | > CFG_NIOS_CPU_ROM_SIZE + GERMS | : | > CONFIG_SYS_NIOS_CPU_ROM_SIZE | : | | = 0x00000800 | : | / - 0x00000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT - 0x00000000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE + 0x00000000 |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_RST_VECT + 0x00000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_ROM_BASE =============================================================================== diff --git a/doc/README.alaska8220 b/doc/README.alaska8220 index 8e659f3..0bd68d9 100644 --- a/doc/README.alaska8220 +++ b/doc/README.alaska8220 @@ -87,12 +87,12 @@ Added files: 3.1 Explanation on NEW definitions in include/configs/alaska8220.h CONFIG_MPC8220 MPC8220 specific CONFIG_ALASKA8220 Alaska board specific - CFG_MPC8220_CLKIN Define Alaska Input Clock + CONFIG_SYS_MPC8220_CLKIN Define Alaska Input Clock CONFIG_PSC_CONSOLE Enable MPC8220 UART CONFIG_EXTUART_CONSOLE Enable External 16552 UART - CFG_AMD_BOOT To determine the u-boot is booted from AMD or Intel - CFG_MBAR MBAR base address - CFG_DEFAULT_MBAR Reset MBAR base address + CONFIG_SYS_AMD_BOOT To determine the u-boot is booted from AMD or Intel + CONFIG_SYS_MBAR MBAR base address + CONFIG_SYS_DEFAULT_MBAR Reset MBAR base address 3.2 Compilation export CROSS_COMPILE=cross-compile-prefix diff --git a/doc/README.cmi b/doc/README.cmi index 884854d..0edd50a 100644 --- a/doc/README.cmi +++ b/doc/README.cmi @@ -35,17 +35,17 @@ Memory Map: Memory Map after relocation: - 0x0000 0000 CFG_SDRAM_BASE + 0x0000 0000 CONFIG_SYS_SDRAM_BASE : 0x000F 9FFF : : - 0x0100 0000 CFG_IMMR (Internal memory map base adress) + 0x0100 0000 CONFIG_SYS_IMMR (Internal memory map base adress) : 0x0130 7FFF : : - 0x0200 0000 CFG_FLASH_BASE + 0x0200 0000 CONFIG_SYS_FLASH_BASE : 0x027C FFFF : diff --git a/doc/README.dk1c20_std32 b/doc/README.dk1c20_std32 index 521fab7..2be1299 100644 --- a/doc/README.dk1c20_std32 +++ b/doc/README.dk1c20_std32 @@ -20,25 +20,25 @@ CPU: "standard_32" no Debug Core On Chip Instrumentation (OCI) enabled - U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000 - CFG_NIOS_CPU_ICACHE = 4096 - CFG_NIOS_CPU_DCACHE = 4096 - CFG_NIOS_CPU_REG_NUMS = 256 - CFG_NIOS_CPU_MUL = 0 - CFG_NIOS_CPU_MSTEP = 1 - CFG_NIOS_CPU_DBG_CORE = 0 + U-Boot CFG: CONFIG_SYS_NIOS_CPU_CLK = 50000000 + CONFIG_SYS_NIOS_CPU_ICACHE = 4096 + CONFIG_SYS_NIOS_CPU_DCACHE = 4096 + CONFIG_SYS_NIOS_CPU_REG_NUMS = 256 + CONFIG_SYS_NIOS_CPU_MUL = 0 + CONFIG_SYS_NIOS_CPU_MSTEP = 1 + CONFIG_SYS_NIOS_CPU_DBG_CORE = 0 OCI: (TODO) IRQ: Nr. | used by ------+-------------------------------------------------------- - 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16 - 25 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 25 - 30 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 30 - 35 | PIO5 | CFG_NIOS_CPU_PIO5_IRQ = 35 - 40 | PIO0 | CFG_NIOS_CPU_PIO0_IRQ = 40 - 45 | ASMI | CFG_NIOS_CPU_ASMI0_IRQ = 45 - 50 | TIMER1 | CFG_NIOS_CPU_TIMER1_IRQ = 50 + 16 | TIMER0 | CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 16 + 25 | UART0 | CONFIG_SYS_NIOS_CPU_UART0_IRQ = 25 + 30 | LAN91C111 | CONFIG_SYS_NIOS_CPU_LAN0_IRQ = 30 + 35 | PIO5 | CONFIG_SYS_NIOS_CPU_PIO5_IRQ = 35 + 40 | PIO0 | CONFIG_SYS_NIOS_CPU_PIO0_IRQ = 40 + 45 | ASMI | CONFIG_SYS_NIOS_CPU_ASMI0_IRQ = 45 + 50 | TIMER1 | CONFIG_SYS_NIOS_CPU_TIMER1_IRQ = 50 MEMORY: 8 MByte Flash 1 MByte SRAM @@ -49,8 +49,8 @@ ASMI: (TODO) <-- ASMI part is 4M bits Timer: TIMER0: high priority programmable timer (IRQ16) TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50) - U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 1 - CFG_NIOS_CPU_USER_TIMER = 0 + U-Boot CFG: CONFIG_SYS_NIOS_CPU_TICK_TIMER = 1 + CONFIG_SYS_NIOS_CPU_USER_TIMER = 0 PIO: Nr. | description ------+-------------------------------------------------------- @@ -63,14 +63,14 @@ PIO: Nr. | description PIO6 | CFPOWER: 1 output to controll CF power supply PIO7 | CFATASEL: 1 output to controll CF ATA card select - U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 0 - CFG_NIOS_CPU_LCD_PIO = 1 - CFG_NIOS_CPU_LED_PIO = 2 - CFG_NIOS_CPU_SEVENSEG_PIO = 3 - CFG_NIOS_CPU_RECONF_PIO = 4 - CFG_NIOS_CPU_CFPRESENT_PIO = 5 - CFG_NIOS_CPU_CFPOWER_PIO = 6 - CFG_NIOS_CPU_CFATASEL_PIO = 7 + U-Boot CFG: CONFIG_SYS_NIOS_CPU_BUTTON_PIO = 0 + CONFIG_SYS_NIOS_CPU_LCD_PIO = 1 + CONFIG_SYS_NIOS_CPU_LED_PIO = 2 + CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO = 3 + CONFIG_SYS_NIOS_CPU_RECONF_PIO = 4 + CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO = 5 + CONFIG_SYS_NIOS_CPU_CFPOWER_PIO = 6 + CONFIG_SYS_NIOS_CPU_CFATASEL_PIO = 7 UART: UART0: fixed baudrate of 115200, fixed protocol 8N1, without handshake RTS/CTS (IRQ25) @@ -91,10 +91,10 @@ IDE: (TODO) 0x02000000 ---32-----------16|15------------0- | : | \ | : | | - SDRAM | : | > CFG_NIOS_CPU_SDRAM_SIZE + SDRAM | : | > CONFIG_SYS_NIOS_CPU_SDRAM_SIZE | : | | = 0x01000000 | : | / - 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SDRAM_BASE + 0x01000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_SDRAM_BASE | | : gap : : : @@ -110,7 +110,7 @@ IDE: (TODO) ASMI i/f : and content : : > 0x________ [5] : unknown) : : | | | | / - 0x00920b00 ---32-----------16|15------------0- CFG_NIOS_CPU_ASMI0 + 0x00920b00 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_ASMI0 | | : gap : | | @@ -120,7 +120,7 @@ IDE: (TODO) IDE i/f : and content : : > 0x00000080 [6] : unknown) : : | | | | / - 0x00920a00 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0 + 0x00920a00 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_IDE0 | (unused) | \ + 0x1c |- - - - - - - - - - - - - - - -| | | (unused) | | @@ -136,7 +136,7 @@ IDE: (TODO) | control (1 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | status (2 bit) (rw) | / - 0x009209e0 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER1 + 0x009209e0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_TIMER1 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO7 | (unused) | | @@ -144,7 +144,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (wo) | / - 0x009209d0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO7 + 0x009209d0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO7 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO6 | (unused) | | @@ -152,7 +152,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (wo) | / - 0x009209c0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO6 + 0x009209c0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO6 | edgecapture (1 bit) (rw) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO5 | interruptmask (1 bit) (rw) | | @@ -160,7 +160,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (ro) | / - 0x009209b0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO5 + 0x009209b0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO5 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO4 | (unused) | | @@ -168,7 +168,7 @@ IDE: (TODO) | direction (1 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (rw) | / - 0x009209a0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO4 + 0x009209a0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO4 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO3 | (unused) | | @@ -176,7 +176,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (16 bit) (wo) | / - 0x00920990 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3 + 0x00920990 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO3 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO2 | (unused) | | @@ -184,7 +184,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (8 bit) (wo) | / - 0x00920980 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2 + 0x00920980 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO2 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO1 | (unused) | | @@ -192,7 +192,7 @@ IDE: (TODO) | direction (11 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (11 bit) (rw) | / - 0x00920970 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1 + 0x00920970 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO1 | edgecapture (4 bit) (rw) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO0 | interruptmask (4 bit) (rw) | | @@ -200,7 +200,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (4 bit) (ro) | / - 0x00920960 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0 + 0x00920960 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO0 | (unused) | \ + 0x1c |- - - - - - - - - - - - - - - -| | | (unused) | | @@ -216,7 +216,7 @@ IDE: (TODO) | control (4 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | status (2 bit) (rw) | / - 0x00920940 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0 + 0x00920940 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_TIMER0 | | \ : gap : > (space for UART1) | | / @@ -236,28 +236,28 @@ IDE: (TODO) | txdata (8 bit) (wo) | | + 0x04 |- - - - - - - - - - - - - - - -| | | rxdata (8 bit) (ro) | / - 0x00920900 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0 + 0x00920900 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_UART0 - - - - - - - - - - - on chip debugging - - - - - - - - - - - - - - - - - - - 0x00920900 ----------------------------------- | | \ : (real size : | - OCI Debug : and content : > CFG_NIOS_CPU_OCI_SIZE + OCI Debug : and content : > CONFIG_SYS_NIOS_CPU_OCI_SIZE : unknown) : | = 0x00000100 | | / - 0x00920800 ----------------------------------- CFG_NIOS_CPU_OCI_BASE + 0x00920800 ----------------------------------- CONFIG_SYS_NIOS_CPU_OCI_BASE - - - - - - - - - - - on chip memory - - - - - - - - - - - 0x00920800 ---32-----------16|15------------0- | : | \ | : | | - GERMS | : | > CFG_NIOS_CPU_ROM_SIZE + GERMS | : | > CONFIG_SYS_NIOS_CPU_ROM_SIZE | : | | = 0x00000800 | : | / - 0x00920000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT - 0x00920000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE + 0x00920000 |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_RST_VECT + 0x00920000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_ROM_BASE - - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - - @@ -279,7 +279,7 @@ IDE: (TODO) | +---------------------------+ | | 0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| | | gap | / - 0x00910000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE + 0x00910000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_LAN0_BASE | | : gap : : : @@ -293,30 +293,30 @@ IDE: (TODO) 0x00900000 --+32-----------16|15------------0+ | : | \ \ | : | | | - | : | | > CFG_NIOS_CPU_VEC_SIZE + | : | | > CONFIG_SYS_NIOS_CPU_VEC_SIZE | : | | | = 0x00000100 | : | | / - 0x008fff00 |- - - - - - - -:- - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE - 0x008fff00 |- - - - - - - -:- - - - - - - -+-|- CFG_NIOS_CPU_STACK + 0x008fff00 |- - - - - - - -:- - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_VEC_BASE + 0x008fff00 |- - - - - - - -:- - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_STACK | : | | \ | : | | | | : | | > stack area | : | | | | : | | V | : | | - SRAM | : | > CFG_NIOS_CPU_SRAM_SIZE + SRAM | : | > CONFIG_SYS_NIOS_CPU_SRAM_SIZE | : | | = 0x00100000 | : | / - 0x00800000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE + 0x00800000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_SRAM_BASE 0x00800000 ---8-------------4|3-------------0- | sector 127 | \ + 0x7f0000 |- - - - - - - - - - - - - - - -| | | : | | - Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE + Flash |- - - - : - - - -| > CONFIG_SYS_NIOS_CPU_FLASH_SIZE | sector 1 : | | = 0x00800000 + 0x010000 |- - - - - - - - - - - - - - - -| | | sector 0 (size = 0x10000) | / - 0x00000000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE + 0x00000000 ---8-------------4|3-------------0- CONFIG_SYS_NIOS_CPU_FLASH_BASE =============================================================================== diff --git a/doc/README.dk1s10_mldk20 b/doc/README.dk1s10_mldk20 index fcf8170..74e07a9 100644 --- a/doc/README.dk1s10_mldk20 +++ b/doc/README.dk1s10_mldk20 @@ -18,29 +18,29 @@ CPU: "LDK2" no Debug Core no On Chip Instrumentation (OCI) - U-Boot CFG: CFG_NIOS_CPU_CLK = 75000000 - CFG_NIOS_CPU_ICACHE = (not present) - CFG_NIOS_CPU_DCACHE = (not present) - CFG_NIOS_CPU_REG_NUMS = 512 - CFG_NIOS_CPU_MUL = 0 - CFG_NIOS_CPU_MSTEP = 1 - CFG_NIOS_CPU_DBG_CORE = 0 + U-Boot CFG: CONFIG_SYS_NIOS_CPU_CLK = 75000000 + CONFIG_SYS_NIOS_CPU_ICACHE = (not present) + CONFIG_SYS_NIOS_CPU_DCACHE = (not present) + CONFIG_SYS_NIOS_CPU_REG_NUMS = 512 + CONFIG_SYS_NIOS_CPU_MUL = 0 + CONFIG_SYS_NIOS_CPU_MSTEP = 1 + CONFIG_SYS_NIOS_CPU_DBG_CORE = 0 IRQ: Nr. | used by ------+-------------------------------------------------------- - 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16 - 17 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 17 - 18 | UART1 | CFG_NIOS_CPU_UART1_IRQ = 18 - 20 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 20 - 25 | IDE0 | CFG_NIOS_CPU_IDE0_IRQ = 25 + 16 | TIMER0 | CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 16 + 17 | UART0 | CONFIG_SYS_NIOS_CPU_UART0_IRQ = 17 + 18 | UART1 | CONFIG_SYS_NIOS_CPU_UART1_IRQ = 18 + 20 | LAN91C111 | CONFIG_SYS_NIOS_CPU_LAN0_IRQ = 20 + 25 | IDE0 | CONFIG_SYS_NIOS_CPU_IDE0_IRQ = 25 MEMORY: 8 MByte Flash 16 MByte SDRAM Timer: TIMER0: high priority programmable timer (IRQ16) - U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 0 - CFG_NIOS_CPU_USER_TIMER = (not present) + U-Boot CFG: CONFIG_SYS_NIOS_CPU_TICK_TIMER = 0 + CONFIG_SYS_NIOS_CPU_USER_TIMER = (not present) PIO: Nr. | description ------+-------------------------------------------------------- @@ -54,14 +54,14 @@ PIO: Nr. | description | CFPRESENT: 1 input for CF present event (IRQ35) | CFATASEL: 1 output to controll CF ATA card select - U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 1 - CFG_NIOS_CPU_LCD_PIO = (not present) - CFG_NIOS_CPU_LED_PIO = (not present) - CFG_NIOS_CPU_SEVENSEG_PIO = (not present) - CFG_NIOS_CPU_RECONF_PIO = (not present) - CFG_NIOS_CPU_CFPRESENT_PIO = (not present) - CFG_NIOS_CPU_CFPOWER_PIO = 0 - CFG_NIOS_CPU_CFATASEL_PIO = (not present) + U-Boot CFG: CONFIG_SYS_NIOS_CPU_BUTTON_PIO = 1 + CONFIG_SYS_NIOS_CPU_LCD_PIO = (not present) + CONFIG_SYS_NIOS_CPU_LED_PIO = (not present) + CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO = (not present) + CONFIG_SYS_NIOS_CPU_RECONF_PIO = (not present) + CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO = (not present) + CONFIG_SYS_NIOS_CPU_CFPOWER_PIO = 0 + CONFIG_SYS_NIOS_CPU_CFATASEL_PIO = (not present) UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, without handshake RTS/CTS (IRQ17) @@ -81,7 +81,7 @@ IDE: (TODO) - - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - - - 0x02000000 ---32-----------16|15------------0- CFG_NIOS_CPU_STACK + 0x02000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_STACK 0x02000000 --+32-----------16|15------------0+ | . | \ \ | . | | | @@ -90,25 +90,25 @@ IDE: (TODO) | . | | V | . | | | . | | - SDRAM | . | > CFG_NIOS_CPU_SDRAM_SIZE + SDRAM | . | > CONFIG_SYS_NIOS_CPU_SDRAM_SIZE | . | | = 0x01000000 | . | | 0x01000100 |- - - - - - - - - - - - - - - -+-|- | . | | \ | . | | | - | . | | > CFG_NIOS_CPU_VEC_SIZE + | . | | > CONFIG_SYS_NIOS_CPU_VEC_SIZE | . | | | = 0x00000100 | | / / - 0x01000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_VEC_BASE - 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SDRAM_BASE + 0x01000000 |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_VEC_BASE + 0x01000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_SDRAM_BASE | sector 127 | \ + 0x7f0000 |- - - - - - - - - - - - - - - -| | | : | | - Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE + Flash |- - - - : - - - -| > CONFIG_SYS_NIOS_CPU_FLASH_SIZE | sector 1 : | | = 0x00800000 + 0x010000 |- - - - - - - - - - - - - - - -| | | sector 0 (size = 0x10000) | / - 0x00800000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE + 0x00800000 ---8-------------4|3-------------0- CONFIG_SYS_NIOS_CPU_FLASH_BASE | | : gap : : : @@ -136,7 +136,7 @@ IDE: (TODO) | +---------------------------+ | | 0x00010300 --+--LAN91C111_REGISTERS_OFFSET---| | | gap | / - 0x00010000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE + 0x00010000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_LAN0_BASE | | : gap : : : @@ -152,7 +152,7 @@ IDE: (TODO) IDE i/f : and content : : > 0x00000080 [5] : unknown) : : | | | | / - 0x00000900 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0 + 0x00000900 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_IDE0 | | \ : gap : > (space for PIO4..7) | | / @@ -172,7 +172,7 @@ IDE: (TODO) | txdata (8 bit) (wo) | | + 0x04 |- - - - - - - - - - - - - - - -| | | rxdata (8 bit) (ro) | / - 0x000008a0 ---32-----------16|15------------0- CFG_NIOS_CPU_UART1 + 0x000008a0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_UART1 | | \ : gap : > (space for PIO2..3) | | / @@ -184,7 +184,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (4 bit) (ro) | / - 0x00000870 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1 + 0x00000870 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO1 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO0 | (unused) | | @@ -192,7 +192,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (wo) | / - 0x00000860 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0 + 0x00000860 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO0 | (unused) | \ + 0x1c |- - - - - - - - - - - - - - - -| | | (unused) | | @@ -208,7 +208,7 @@ IDE: (TODO) | control (4 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | status (2 bit) (rw) | / - 0x00000840 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0 + 0x00000840 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_TIMER0 | | \ : gap : > (space for UART2) | | / @@ -228,18 +228,18 @@ IDE: (TODO) | txdata (8 bit) (wo) | | + 0x04 |- - - - - - - - - - - - - - - -| | | rxdata (8 bit) (ro) | / - 0x00000800 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0 + 0x00000800 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_UART0 - - - - - - - - - - - on chip memory 1 - - - - - - - - - - - 0x00000800 ---32-----------16|15------------0- | : | \ | : | | - GERMS | : | > CFG_NIOS_CPU_ROM_SIZE + GERMS | : | > CONFIG_SYS_NIOS_CPU_ROM_SIZE | : | | = 0x00000800 | : | / - 0x00000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT - 0x00000000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE + 0x00000000 |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_RST_VECT + 0x00000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_ROM_BASE =============================================================================== F L A S H M E M O R Y A L L O C A T I O N diff --git a/doc/README.dk1s10_std32 b/doc/README.dk1s10_std32 index d649eb3..622b2b9 100644 --- a/doc/README.dk1s10_std32 +++ b/doc/README.dk1s10_std32 @@ -19,24 +19,24 @@ CPU: "standard_32" no Debug Core On Chip Instrumentation (OCI) enabled - U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000 - CFG_NIOS_CPU_ICACHE = 4096 - CFG_NIOS_CPU_DCACHE = 4096 - CFG_NIOS_CPU_REG_NUMS = 256 - CFG_NIOS_CPU_MUL = 0 - CFG_NIOS_CPU_MSTEP = 1 - CFG_NIOS_CPU_DBG_CORE = 0 + U-Boot CFG: CONFIG_SYS_NIOS_CPU_CLK = 50000000 + CONFIG_SYS_NIOS_CPU_ICACHE = 4096 + CONFIG_SYS_NIOS_CPU_DCACHE = 4096 + CONFIG_SYS_NIOS_CPU_REG_NUMS = 256 + CONFIG_SYS_NIOS_CPU_MUL = 0 + CONFIG_SYS_NIOS_CPU_MSTEP = 1 + CONFIG_SYS_NIOS_CPU_DBG_CORE = 0 OCI: (TODO) IRQ: Nr. | used by ------+-------------------------------------------------------- - 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16 - 25 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 25 - 30 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 30 - 35 | PIO5 | CFG_NIOS_CPU_PIO5_IRQ = 35 - 40 | PIO0 | CFG_NIOS_CPU_PIO0_IRQ = 40 - 50 | TIMER1 | CFG_NIOS_CPU_TIMER1_IRQ = 50 + 16 | TIMER0 | CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 16 + 25 | UART0 | CONFIG_SYS_NIOS_CPU_UART0_IRQ = 25 + 30 | LAN91C111 | CONFIG_SYS_NIOS_CPU_LAN0_IRQ = 30 + 35 | PIO5 | CONFIG_SYS_NIOS_CPU_PIO5_IRQ = 35 + 40 | PIO0 | CONFIG_SYS_NIOS_CPU_PIO0_IRQ = 40 + 50 | TIMER1 | CONFIG_SYS_NIOS_CPU_TIMER1_IRQ = 50 MEMORY: 8 MByte Flash 1 MByte SRAM @@ -45,8 +45,8 @@ MEMORY: 8 MByte Flash Timer: TIMER0: high priority programmable timer (IRQ16) TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50) - U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 1 - CFG_NIOS_CPU_USER_TIMER = 0 + U-Boot CFG: CONFIG_SYS_NIOS_CPU_TICK_TIMER = 1 + CONFIG_SYS_NIOS_CPU_USER_TIMER = 0 PIO: Nr. | description ------+-------------------------------------------------------- @@ -59,14 +59,14 @@ PIO: Nr. | description PIO6 | CFPOWER: 1 output to controll CF power supply PIO7 | CFATASEL: 1 output to controll CF ATA card select - U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 0 - CFG_NIOS_CPU_LCD_PIO = 1 - CFG_NIOS_CPU_LED_PIO = 2 - CFG_NIOS_CPU_SEVENSEG_PIO = 3 - CFG_NIOS_CPU_RECONF_PIO = 4 - CFG_NIOS_CPU_CFPRESENT_PIO = 5 - CFG_NIOS_CPU_CFPOWER_PIO = 6 - CFG_NIOS_CPU_CFATASEL_PIO = 7 + U-Boot CFG: CONFIG_SYS_NIOS_CPU_BUTTON_PIO = 0 + CONFIG_SYS_NIOS_CPU_LCD_PIO = 1 + CONFIG_SYS_NIOS_CPU_LED_PIO = 2 + CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO = 3 + CONFIG_SYS_NIOS_CPU_RECONF_PIO = 4 + CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO = 5 + CONFIG_SYS_NIOS_CPU_CFPOWER_PIO = 6 + CONFIG_SYS_NIOS_CPU_CFATASEL_PIO = 7 UART: UART0: fixed baudrate of 115200, fixed protocol 8N1, without handshake RTS/CTS (IRQ25) @@ -87,10 +87,10 @@ IDE: (TODO) 0x02000000 ---32-----------16|15------------0- | : | \ | : | | - SDRAM | : | > CFG_NIOS_CPU_SDRAM_SIZE + SDRAM | : | > CONFIG_SYS_NIOS_CPU_SDRAM_SIZE | : | | = 0x01000000 | : | / - 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SDRAM_BASE + 0x01000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_SDRAM_BASE | | : gap : : : @@ -106,7 +106,7 @@ IDE: (TODO) IDE i/f : and content : : > 0x00000080 [5] : unknown) : : | | | | / - 0x00920a00 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0 + 0x00920a00 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_IDE0 | (unused) | \ + 0x1c |- - - - - - - - - - - - - - - -| | | (unused) | | @@ -122,7 +122,7 @@ IDE: (TODO) | control (1 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | status (2 bit) (rw) | / - 0x009209e0 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER1 + 0x009209e0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_TIMER1 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO7 | (unused) | | @@ -130,7 +130,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (wo) | / - 0x009209d0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO7 + 0x009209d0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO7 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO6 | (unused) | | @@ -138,7 +138,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (wo) | / - 0x009209c0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO6 + 0x009209c0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO6 | edgecapture (1 bit) (rw) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO5 | interruptmask (1 bit) (rw) | | @@ -146,7 +146,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (ro) | / - 0x009209b0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO5 + 0x009209b0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO5 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO4 | (unused) | | @@ -154,7 +154,7 @@ IDE: (TODO) | direction (1 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (rw) | / - 0x009209a0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO4 + 0x009209a0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO4 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO3 | (unused) | | @@ -162,7 +162,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (16 bit) (wo) | / - 0x00920990 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3 + 0x00920990 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO3 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO2 | (unused) | | @@ -170,7 +170,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (8 bit) (wo) | / - 0x00920980 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2 + 0x00920980 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO2 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO1 | (unused) | | @@ -178,7 +178,7 @@ IDE: (TODO) | direction (11 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (11 bit) (rw) | / - 0x00920970 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1 + 0x00920970 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO1 | edgecapture (4 bit) (rw) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO0 | interruptmask (4 bit) (rw) | | @@ -186,7 +186,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (4 bit) (ro) | / - 0x00920960 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0 + 0x00920960 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO0 | (unused) | \ + 0x1c |- - - - - - - - - - - - - - - -| | | (unused) | | @@ -202,7 +202,7 @@ IDE: (TODO) | control (4 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | status (2 bit) (rw) | / - 0x00920940 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0 + 0x00920940 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_TIMER0 | | \ : gap : > (space for UART1) | | / @@ -222,28 +222,28 @@ IDE: (TODO) | txdata (8 bit) (wo) | | + 0x04 |- - - - - - - - - - - - - - - -| | | rxdata (8 bit) (ro) | / - 0x00920900 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0 + 0x00920900 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_UART0 - - - - - - - - - - - on chip debugging - - - - - - - - - - - - - - - - - - - 0x00920900 ----------------------------------- | | \ : (real size : | - OCI Debug : and content : > CFG_NIOS_CPU_OCI_SIZE + OCI Debug : and content : > CONFIG_SYS_NIOS_CPU_OCI_SIZE : unknown) : | = 0x00000100 | | / - 0x00920800 ----------------------------------- CFG_NIOS_CPU_OCI_BASE + 0x00920800 ----------------------------------- CONFIG_SYS_NIOS_CPU_OCI_BASE - - - - - - - - - - - on chip memory 2 - - - - - - - - - - - 0x00920800 ---32-----------16|15------------0- | : | \ | : | | - GERMS | : | > CFG_NIOS_CPU_ROM_SIZE + GERMS | : | > CONFIG_SYS_NIOS_CPU_ROM_SIZE | : | | = 0x00000800 | : | / - 0x00920000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT - 0x00920000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE + 0x00920000 |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_RST_VECT + 0x00920000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_ROM_BASE - - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - - @@ -265,17 +265,17 @@ IDE: (TODO) | +---------------------------+ | | 0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| | | gap | / - 0x00910000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE + 0x00910000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_LAN0_BASE - - - - - - - - - - - on chip memory 1 - - - - - - - - - - - 0x00910000 ---32-----------16|15------------0- | : | \ | : | | - onchip RAM | : | > CFG_NIOS_CPU_RAM_SIZE + onchip RAM | : | > CONFIG_SYS_NIOS_CPU_RAM_SIZE | : | | = 0x00010000 | : | / - 0x00900000 ---32-----------16|15------------0- CFG_NIOS_CPU_RAM_BASE + 0x00900000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_RAM_BASE - - - - - - - - - - - external memory 1 - - - - - - - - - - - - - - - - - - - @@ -283,30 +283,30 @@ IDE: (TODO) 0x00900000 --+32-----------16|15------------0+ | . | \ \ | . | | | - | . | | > CFG_NIOS_CPU_VEC_SIZE + | . | | > CONFIG_SYS_NIOS_CPU_VEC_SIZE | . | | | = 0x00000100 | . | | / - 0x008fff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE - 0x008fff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_STACK + 0x008fff00 |- - - - - - - - - - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_VEC_BASE + 0x008fff00 |- - - - - - - - - - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_STACK | . | | \ | . | | | | . | | > stack area | . | | | | . | | V | . | | - SRAM | . | > CFG_NIOS_CPU_SRAM_SIZE + SRAM | . | > CONFIG_SYS_NIOS_CPU_SRAM_SIZE | . | | = 0x00100000 | | / - 0x00800000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE + 0x00800000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_SRAM_BASE 0x00800000 ---8-------------4|3-------------0- | sector 127 | \ + 0x7f0000 |- - - - - - - - - - - - - - - -| | | : | | - Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE + Flash |- - - - : - - - -| > CONFIG_SYS_NIOS_CPU_FLASH_SIZE | sector 1 : | | = 0x00800000 + 0x010000 |- - - - - - - - - - - - - - - -| | | sector 0 (size = 0x10000) | / - 0x00000000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE + 0x00000000 ---8-------------4|3-------------0- CONFIG_SYS_NIOS_CPU_FLASH_BASE =============================================================================== diff --git a/doc/README.dk1s40_std32 b/doc/README.dk1s40_std32 index 08c8244..9a0ea06 100644 --- a/doc/README.dk1s40_std32 +++ b/doc/README.dk1s40_std32 @@ -19,24 +19,24 @@ CPU: "standard_32" no Debug Core On Chip Instrumentation (OCI) enabled - U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000 - CFG_NIOS_CPU_ICACHE = 4096 - CFG_NIOS_CPU_DCACHE = 4096 - CFG_NIOS_CPU_REG_NUMS = 256 - CFG_NIOS_CPU_MUL = 0 - CFG_NIOS_CPU_MSTEP = 1 - CFG_NIOS_CPU_DBG_CORE = 0 + U-Boot CFG: CONFIG_SYS_NIOS_CPU_CLK = 50000000 + CONFIG_SYS_NIOS_CPU_ICACHE = 4096 + CONFIG_SYS_NIOS_CPU_DCACHE = 4096 + CONFIG_SYS_NIOS_CPU_REG_NUMS = 256 + CONFIG_SYS_NIOS_CPU_MUL = 0 + CONFIG_SYS_NIOS_CPU_MSTEP = 1 + CONFIG_SYS_NIOS_CPU_DBG_CORE = 0 OCI: (TODO) IRQ: Nr. | used by ------+-------------------------------------------------------- - 16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16 - 25 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 25 - 30 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 30 - 35 | PIO5 | CFG_NIOS_CPU_PIO5_IRQ = 35 - 40 | PIO0 | CFG_NIOS_CPU_PIO0_IRQ = 40 - 50 | TIMER1 | CFG_NIOS_CPU_TIMER1_IRQ = 50 + 16 | TIMER0 | CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 16 + 25 | UART0 | CONFIG_SYS_NIOS_CPU_UART0_IRQ = 25 + 30 | LAN91C111 | CONFIG_SYS_NIOS_CPU_LAN0_IRQ = 30 + 35 | PIO5 | CONFIG_SYS_NIOS_CPU_PIO5_IRQ = 35 + 40 | PIO0 | CONFIG_SYS_NIOS_CPU_PIO0_IRQ = 40 + 50 | TIMER1 | CONFIG_SYS_NIOS_CPU_TIMER1_IRQ = 50 MEMORY: 8 MByte Flash 1 MByte SRAM @@ -45,8 +45,8 @@ MEMORY: 8 MByte Flash Timer: TIMER0: high priority programmable timer (IRQ16) TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50) - U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 1 - CFG_NIOS_CPU_USER_TIMER = 0 + U-Boot CFG: CONFIG_SYS_NIOS_CPU_TICK_TIMER = 1 + CONFIG_SYS_NIOS_CPU_USER_TIMER = 0 PIO: Nr. | description ------+-------------------------------------------------------- @@ -59,14 +59,14 @@ PIO: Nr. | description PIO6 | CFPOWER: 1 output to controll CF power supply PIO7 | CFATASEL: 1 output to controll CF ATA card select - U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 0 - CFG_NIOS_CPU_LCD_PIO = 1 - CFG_NIOS_CPU_LED_PIO = 2 - CFG_NIOS_CPU_SEVENSEG_PIO = 3 - CFG_NIOS_CPU_RECONF_PIO = 4 - CFG_NIOS_CPU_CFPRESENT_PIO = 5 - CFG_NIOS_CPU_CFPOWER_PIO = 6 - CFG_NIOS_CPU_CFATASEL_PIO = 7 + U-Boot CFG: CONFIG_SYS_NIOS_CPU_BUTTON_PIO = 0 + CONFIG_SYS_NIOS_CPU_LCD_PIO = 1 + CONFIG_SYS_NIOS_CPU_LED_PIO = 2 + CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO = 3 + CONFIG_SYS_NIOS_CPU_RECONF_PIO = 4 + CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO = 5 + CONFIG_SYS_NIOS_CPU_CFPOWER_PIO = 6 + CONFIG_SYS_NIOS_CPU_CFATASEL_PIO = 7 UART: UART0: fixed baudrate of 115200, fixed protocol 8N1, without handshake RTS/CTS (IRQ25) @@ -87,10 +87,10 @@ IDE: (TODO) 0x02000000 ---32-----------16|15------------0- | : | \ | : | | - SDRAM | : | > CFG_NIOS_CPU_SRAM_SIZE + SDRAM | : | > CONFIG_SYS_NIOS_CPU_SRAM_SIZE | : | | = 0x01000000 | : | / - 0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE + 0x01000000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_SRAM_BASE | | : gap : : : @@ -106,7 +106,7 @@ IDE: (TODO) IDE i/f : and content : : > 0x00000080 [5] : unknown) : : | | | | / - 0x00920a00 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0 + 0x00920a00 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_IDE0 | (unused) | \ + 0x1c |- - - - - - - - - - - - - - - -| | | (unused) | | @@ -122,7 +122,7 @@ IDE: (TODO) | control (1 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | status (2 bit) (rw) | / - 0x009209e0 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER1 + 0x009209e0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_TIMER1 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO7 | (unused) | | @@ -130,7 +130,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (wo) | / - 0x009209d0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO7 + 0x009209d0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO7 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO6 | (unused) | | @@ -138,7 +138,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (wo) | / - 0x009209c0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO6 + 0x009209c0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO6 | edgecapture (1 bit) (rw) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO5 | interruptmask (1 bit) (rw) | | @@ -146,7 +146,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (ro) | / - 0x009209b0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO5 + 0x009209b0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO5 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO4 | (unused) | | @@ -154,7 +154,7 @@ IDE: (TODO) | direction (1 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (1 bit) (rw) | / - 0x009209a0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO4 + 0x009209a0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO4 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO3 | (unused) | | @@ -162,7 +162,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (16 bit) (wo) | / - 0x00920990 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3 + 0x00920990 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO3 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO2 | (unused) | | @@ -170,7 +170,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (8 bit) (wo) | / - 0x00920980 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2 + 0x00920980 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO2 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO1 | (unused) | | @@ -178,7 +178,7 @@ IDE: (TODO) | direction (11 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (11 bit) (rw) | / - 0x00920970 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1 + 0x00920970 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO1 | edgecapture (4 bit) (rw) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO0 | interruptmask (4 bit) (rw) | | @@ -186,7 +186,7 @@ IDE: (TODO) | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (4 bit) (ro) | / - 0x00920960 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0 + 0x00920960 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO0 | (unused) | \ + 0x1c |- - - - - - - - - - - - - - - -| | | (unused) | | @@ -202,7 +202,7 @@ IDE: (TODO) | control (4 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | status (2 bit) (rw) | / - 0x00920940 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0 + 0x00920940 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_TIMER0 | | \ : gap : > (space for UART1) | | / @@ -222,28 +222,28 @@ IDE: (TODO) | txdata (8 bit) (wo) | | + 0x04 |- - - - - - - - - - - - - - - -| | | rxdata (8 bit) (ro) | / - 0x00920900 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0 + 0x00920900 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_UART0 - - - - - - - - - - - on chip debugging - - - - - - - - - - - - - - - - - - - 0x00920900 ----------------------------------- | | \ : (real size : | - OCI Debug : and content : > CFG_NIOS_CPU_OCI_SIZE + OCI Debug : and content : > CONFIG_SYS_NIOS_CPU_OCI_SIZE : unknown) : | = 0x00000100 | | / - 0x00920800 ----------------------------------- CFG_NIOS_CPU_OCI_BASE + 0x00920800 ----------------------------------- CONFIG_SYS_NIOS_CPU_OCI_BASE - - - - - - - - - - - on chip memory 2 - - - - - - - - - - - 0x00920800 ---32-----------16|15------------0- | : | \ | : | | - GERMS | : | > CFG_NIOS_CPU_ROM_SIZE + GERMS | : | > CONFIG_SYS_NIOS_CPU_ROM_SIZE | : | | = 0x00000800 | : | / - 0x00920000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT - 0x00920000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE + 0x00920000 |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_RST_VECT + 0x00920000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_ROM_BASE - - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - - @@ -265,17 +265,17 @@ IDE: (TODO) | +---------------------------+ | | 0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| | | gap | / - 0x00910000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE + 0x00910000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_LAN0_BASE - - - - - - - - - - - on chip memory 1 - - - - - - - - - - - 0x00910000 ---32-----------16|15------------0- | : | \ | : | | - onchip RAM | : | > CFG_NIOS_CPU_RAM_SIZE + onchip RAM | : | > CONFIG_SYS_NIOS_CPU_RAM_SIZE | : | | = 0x00010000 | : | / - 0x00900000 ---32-----------16|15------------0- CFG_NIOS_CPU_RAM_BASE + 0x00900000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_RAM_BASE - - - - - - - - - - - external memory 1 - - - - - - - - - - - - - - - - - - - @@ -283,30 +283,30 @@ IDE: (TODO) 0x00900000 --+32-----------16|15------------0+ | . | \ \ | . | | | - | . | | > CFG_NIOS_CPU_VEC_SIZE + | . | | > CONFIG_SYS_NIOS_CPU_VEC_SIZE | . | | | = 0x00000100 | . | | / - 0x008fff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE - 0x008fff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_STACK + 0x008fff00 |- - - - - - - - - - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_VEC_BASE + 0x008fff00 |- - - - - - - - - - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_STACK | . | | \ | . | | | | . | | > stack area | . | | | | . | | V | . | | - SRAM | . | > CFG_NIOS_CPU_SRAM_SIZE + SRAM | . | > CONFIG_SYS_NIOS_CPU_SRAM_SIZE | . | | = 0x00100000 | | / - 0x00800000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE + 0x00800000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_SRAM_BASE 0x00800000 ---8-------------4|3-------------0- | sector 127 | \ + 0x7f0000 |- - - - - - - - - - - - - - - -| | | : | | - Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE + Flash |- - - - : - - - -| > CONFIG_SYS_NIOS_CPU_FLASH_SIZE | sector 1 : | | = 0x00800000 + 0x010000 |- - - - - - - - - - - - - - - -| | | sector 0 (size = 0x10000) | / - 0x00000000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE + 0x00000000 ---8-------------4|3-------------0- CONFIG_SYS_NIOS_CPU_FLASH_BASE =============================================================================== diff --git a/doc/README.dk20k200_std32 b/doc/README.dk20k200_std32 index 7b5d4d4..fc2d2a3 100644 --- a/doc/README.dk20k200_std32 +++ b/doc/README.dk20k200_std32 @@ -15,20 +15,20 @@ CPU: "standard_32" no Debug Core no On Chip Instrumentation (OCI) enabled - U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000 - CFG_NIOS_CPU_ICACHE = 0 - CFG_NIOS_CPU_DCACHE = 0 - CFG_NIOS_CPU_REG_NUMS = 256 - CFG_NIOS_CPU_MUL = 0 - CFG_NIOS_CPU_MSTEP = 1 - CFG_NIOS_CPU_DBG_CORE = 0 + U-Boot CFG: CONFIG_SYS_NIOS_CPU_CLK = 50000000 + CONFIG_SYS_NIOS_CPU_ICACHE = 0 + CONFIG_SYS_NIOS_CPU_DCACHE = 0 + CONFIG_SYS_NIOS_CPU_REG_NUMS = 256 + CONFIG_SYS_NIOS_CPU_MUL = 0 + CONFIG_SYS_NIOS_CPU_MSTEP = 1 + CONFIG_SYS_NIOS_CPU_DBG_CORE = 0 IRQ: Nr. | used by ------+-------------------------------------------------------- - 25 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 25 - 26 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 26 - 27 | PIO2 | CFG_NIOS_CPU_PIO2_IRQ = 27 - 28 | UART1 | CFG_NIOS_CPU_UART1_IRQ = 28 (debug) + 25 | TIMER0 | CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 25 + 26 | UART0 | CONFIG_SYS_NIOS_CPU_UART0_IRQ = 26 + 27 | PIO2 | CONFIG_SYS_NIOS_CPU_PIO2_IRQ = 27 + 28 | UART1 | CONFIG_SYS_NIOS_CPU_UART1_IRQ = 28 (debug) MEMORY: 1 MByte Flash 256 KByte SRAM @@ -36,7 +36,7 @@ MEMORY: 1 MByte Flash Timer: TIMER0: high priority programmable timer (IRQ25) - U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 0 + U-Boot CFG: CONFIG_SYS_NIOS_CPU_TICK_TIMER = 0 PIO: Nr. | description ------+-------------------------------------------------------- @@ -45,10 +45,10 @@ PIO: Nr. | description PIO2 | BUTTON: 4 inputs for user push buttons (IRQ27) PIO3 | LCD: 11 in/outputs for ASCII LCD - U-Boot CFG: CFG_NIOS_CPU_SEVENSEG_PIO = 0 - CFG_NIOS_CPU_LED_PIO = 1 - CFG_NIOS_CPU_BUTTON_PIO = 2 - CFG_NIOS_CPU_LCD_PIO = 3 + U-Boot CFG: CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO = 0 + CONFIG_SYS_NIOS_CPU_LED_PIO = 1 + CONFIG_SYS_NIOS_CPU_BUTTON_PIO = 2 + CONFIG_SYS_NIOS_CPU_LCD_PIO = 3 UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, without handshake RTS/CTS (IRQ26) @@ -70,7 +70,7 @@ UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, | sector 5 : | | + 0x020000 |- - - - - - - - -| | | sector 4 (size = 0x10000) | | - + 0x010000 |- - - - - - - - - - - - - - - -| > CFG_NIOS_CPU_FLASH_SIZE + + 0x010000 |- - - - - - - - - - - - - - - -| > CONFIG_SYS_NIOS_CPU_FLASH_SIZE | sector 3 (size = 0x08000) | | = 0x00100000 + 0x008000 |- - - - - - - - - - - - - - - -| | | sector 2 (size = 0x02000) | | @@ -78,7 +78,7 @@ UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, | sector 1 (size = 0x02000) | | + 0x004000 |- - - - - - - - - - - - - - - -| | | sector 0 (size = 0x04000) | / - 0x00100000 ---15------------8|7-------------0- CFG_NIOS_CPU_FLASH_BASE + 0x00100000 ---15------------8|7-------------0- CONFIG_SYS_NIOS_CPU_FLASH_BASE | | : gap : | | @@ -86,21 +86,21 @@ UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, 0x00080000 --+32-----------16|15------------0+ | . | \ \ | . | | | - | . | | > CFG_NIOS_CPU_VEC_SIZE + | . | | > CONFIG_SYS_NIOS_CPU_VEC_SIZE | . | | | = 0x00000100 | . | | / - 0x0007ff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE - 0x0007ff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_STACK + 0x0007ff00 |- - - - - - - - - - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_VEC_BASE + 0x0007ff00 |- - - - - - - - - - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_STACK | . | | \ | . | | | | . | | > stack area | . | | | | . | | V | . | | - SRAM | . | > CFG_NIOS_CPU_SRAM_SIZE + SRAM | . | > CONFIG_SYS_NIOS_CPU_SRAM_SIZE | . | | = 0x00040000 | | / - 0x00040000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE + 0x00040000 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_SRAM_BASE | | : gap : : : @@ -126,7 +126,7 @@ UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, | txdata (8 bit) (wo) | | + 0x04 |- - - - - - - - - - - - - - - -| | | rxdata (8 bit) (ro) | / - 0x000004c0 ---32-----------16|15------------0- CFG_NIOS_CPU_UART1 + 0x000004c0 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_UART1 | | : gap : | | @@ -138,7 +138,7 @@ UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, | direction (11 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (11 bit) (rw) | / - 0x00000480 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3 + 0x00000480 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO3 | edgecapture (12 bit) (rw) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO2 | interruptmask (12 bit) (rw) | | @@ -146,7 +146,7 @@ UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (12 bit) (ro) | / - 0x00000470 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2 + 0x00000470 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO2 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO1 | (unused) | | @@ -154,7 +154,7 @@ UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, | direction (2 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (2 bit) (rw) | / - 0x00000460 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1 + 0x00000460 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO1 | (unused) | \ + 0x1c |- - - - - - - - - - - - - - - -| | | (unused) | | @@ -170,7 +170,7 @@ UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, | control (4 bit) (rw) | | + 0x04 |- - - - - - - - - - - - - - - -| | | status (2 bit) (rw) | / - 0x00000440 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0 + 0x00000440 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_TIMER0 | (unused) | \ + 0x0c |- - - - - - - - - - - - - - - -| | PIO0 | (unused) | | @@ -178,7 +178,7 @@ UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, | (unused) | | + 0x04 |- - - - - - - - - - - - - - - -| | | data (16 bit) (wo) | / - 0x00000420 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0 + 0x00000420 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_PIO0 | (unused) | \ + 0x1c |- - - - - - - - - - - - - - - -| | | (unused) | | @@ -194,7 +194,7 @@ UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, | txdata (8 bit) (wo) | | + 0x04 |- - - - - - - - - - - - - - - -| | | rxdata (8 bit) (ro) | / - 0x00000400 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0 + 0x00000400 ---32-----------16|15------------0- CONFIG_SYS_NIOS_CPU_UART0 - - - - - - - - - - - on chip memory - - - - - - - - - - - diff --git a/doc/README.ebony b/doc/README.ebony index 8b030db..a395a49 100644 --- a/doc/README.ebony +++ b/doc/README.ebony @@ -35,7 +35,7 @@ I2C iprobe ===================== The i2c utilities have been tested on both Rev B. and Rev C. and -look good. The CFG_I2C_NOPROBES macro is defined to prevent +look good. The CONFIG_SYS_I2C_NOPROBES macro is defined to prevent probing the CDCV850 clock controller at address 0x69 (since reading it causes the i2c implementation to misbehave. The output of iprobe should look like this (assuming you are only using a single diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr new file mode 100644 index 0000000..9c2224f --- /dev/null +++ b/doc/README.fsl-ddr @@ -0,0 +1,69 @@ + +Table of interleaving modes supported in cpu/8xxx/ddr/ +====================================================== + +-------------+---------------------------------------------------------+ + | | Rank Interleaving | + | +--------+-----------+-----------+------------+-----------+ + |Memory | | | | 2x2 | 4x1 | + |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ | + |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} | + +-------------+--------+-----------+-----------+------------+-----------+ + |None | Yes | Yes | Yes | Yes | Yes | + +-------------+--------+-----------+-----------+------------+-----------+ + |Cacheline | Yes | Yes | No | No, Only(*)| Yes | + | |CS0 Only| | | {CS0+CS1} | | + +-------------+--------+-----------+-----------+------------+-----------+ + |Page | Yes | Yes | No | No, Only(*)| Yes | + | |CS0 Only| | | {CS0+CS1} | | + +-------------+--------+-----------+-----------+------------+-----------+ + |Bank | Yes | Yes | No | No, Only(*)| Yes | + | |CS0 Only| | | {CS0+CS1} | | + +-------------+--------+-----------+-----------+------------+-----------+ + |Superbank | No | Yes | No | No, Only(*)| Yes | + | | | | | {CS0+CS1} | | + +-------------+--------+-----------+-----------+------------+-----------+ + (*) Although the hardware can be configured with memory controller + interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1} + from each controller. {CS2+CS3} on each controller are only rank + interleaved on that controller. + +The ways to configure the ddr interleaving mode +============================================== +1. In board header file(e.g.MPC8572DS.h), add default interleaving setting + under "CONFIG_EXTRA_ENV_SETTINGS", like: + #define CONFIG_EXTRA_ENV_SETTINGS \ + "memctl_intlv_ctl=2\0" \ + ...... + +2. Run u-boot "setenv" command to configure the memory interleaving mode. + Either numerical or string value is accepted. + + # disable memory controller interleaving + setenv memctl_intlv_ctl + + # cacheline interleaving + setenv memctl_intlv_ctl 0 or setenv memctl_intlv_ctl cacheline + + # page interleaving + setenv memctl_intlv_ctl 1 or setenv memctl_intlv_ctl page + + # bank interleaving + setenv memctl_intlv_ctl 2 or setenv memctl_intlv_ctl bank + + # superbank + setenv memctl_intlv_ctl 3 or setenv memctl_intlv_ctl superbank + + # disable bank (chip-select) interleaving + setenv ba_intlv_ctl + + # bank(chip-select) interleaving cs0+cs1 + setenv ba_intlv_ctl 0x40 or setenv ba_intlv_ctl cs0_cs1 + + # bank(chip-select) interleaving cs2+cs3 + setenv ba_intlv_ctl 0x20 or setenv ba_intlv_ctl cs2_cs3 + + # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2) + setenv ba_intlv_ctl 0x60 or setenv ba_intlv_ctl cs0_cs1_and_cs2_cs3 + + # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1) + setenv ba_intlv_ctl 0x04 or setenv ba_intlv_ctl cs0_cs1_cs2_cs3 diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci index 147ea51..ba7cea8 100644 --- a/doc/README.generic_usb_ohci +++ b/doc/README.generic_usb_ohci @@ -11,24 +11,24 @@ Configuration options CONFIG_USB_OHCI_NEW: enable the new OHCI driver - CFG_USB_OHCI_BOARD_INIT: call the board dependant hooks: + CONFIG_SYS_USB_OHCI_BOARD_INIT: call the board dependant hooks: - extern int usb_board_init(void); - extern int usb_board_stop(void); - extern int usb_cpu_init_fail(void); - CFG_USB_OHCI_CPU_INIT: call the cpu dependant hooks: + CONFIG_SYS_USB_OHCI_CPU_INIT: call the cpu dependant hooks: - extern int usb_cpu_init(void); - extern int usb_cpu_stop(void); - extern int usb_cpu_init_fail(void); - CFG_USB_OHCI_REGS_BASE: defines the base address of the OHCI + CONFIG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI registers - CFG_USB_OHCI_SLOT_NAME: slot name + CONFIG_SYS_USB_OHCI_SLOT_NAME: slot name - CFG_USB_OHCI_MAX_ROOT_PORTS: maximal number of ports of the + CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS: maximal number of ports of the root hub. @@ -39,7 +39,7 @@ The USB bus operates in little endian, but unfortunately there are OHCI controllers that operate in big endian such as ppc4xx and mpc5xxx. For these the config option - CFG_OHCI_BE_CONTROLLER + CONFIG_SYS_OHCI_BE_CONTROLLER needs to be defined. @@ -60,4 +60,4 @@ If undefined, the first instance found in PCI space will be used. PCI Controllers need to do byte swapping on register accesses, so they should to define: - CFG_OHCI_SWAP_REG_ACCESS + CONFIG_SYS_OHCI_SWAP_REG_ACCESS diff --git a/doc/README.lynxkdi b/doc/README.lynxkdi index 8fdf495..076f018 100644 --- a/doc/README.lynxkdi +++ b/doc/README.lynxkdi @@ -39,9 +39,9 @@ modifications to the config file. Edit include/configs/MPC8260ADS.h to use the following: -#define CFG_IMMR 0xFA200000 -#define CFG_BCSR 0xFA100000 -#define CFG_BR1_PRELIM 0xFA101801 +#define CONFIG_SYS_IMMR 0xFA200000 +#define CONFIG_SYS_BCSR 0xFA100000 +#define CONFIG_SYS_BR1_PRELIM 0xFA101801 When creating a LynxOS or BlueCat u-boot image using mkimage, you must specify the following: diff --git a/doc/README.m52277evb b/doc/README.m52277evb index de1daba..e002947 100644 --- a/doc/README.m52277evb +++ b/doc/README.m52277evb @@ -70,12 +70,12 @@ CONFIG_M52277 -- define for all Freescale MCF52277 CPUs CONFIG_M52277EVB -- define for M52277EVB board CONFIG_MCFUART -- define to use common CF Uart driver -CFG_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 CONFIG_BAUDRATE -- define UART baudrate CONFIG_MCFRTC -- define to use common CF RTC driver -CFG_MCFRTC_BASE -- provide base address for RTC in immap.h -CFG_RTC_OSCILLATOR -- define RTC clock frequency +CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h +CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency RTC_DEBUG -- define to show RTC debug message CONFIG_CMD_DATE -- enable to use date feature in u-boot @@ -85,22 +85,22 @@ CONFIG_MCFPIT -- define to use PIT timer CONFIG_FSL_I2C -- define to use FSL common I2C driver CONFIG_HARD_I2C -- define for I2C hardware support CONFIG_SOFT_I2C -- define for I2C bit-banged -CFG_I2C_SPEED -- define for I2C speed -CFG_I2C_SLAVE -- define for I2C slave address -CFG_I2C_OFFSET -- define for I2C base address offset -CFG_IMMR -- define for MBAR offset +CONFIG_SYS_I2C_SPEED -- define for I2C speed +CONFIG_SYS_I2C_SLAVE -- define for I2C slave address +CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset +CONFIG_SYS_IMMR -- define for MBAR offset -CFG_MBAR -- define MBAR offset +CONFIG_SYS_MBAR -- define MBAR offset CONFIG_MONITOR_IS_IN_RAM -- Not support -CFG_INIT_RAM_ADDR -- defines the base address of the MCF52277 internal SRAM +CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF52277 internal SRAM -CFG_CSn_BASE -- defines the Chip Select Base register -CFG_CSn_MASK -- defines the Chip Select Mask register -CFG_CSn_CTRL -- defines the Chip Select Control register +CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register +CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register +CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register -CFG_SDRAM_BASE -- defines the DRAM Base +CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base CONFIG_LCD and CONFIG_CMD_USB are not supported in this current u-boot, update will be provided at later time diff --git a/doc/README.m5253evbe b/doc/README.m5253evbe index 0426cb1..f51609f 100644 --- a/doc/README.m5253evbe +++ b/doc/README.m5253evbe @@ -28,9 +28,9 @@ Created 06/05/2007 CONFIG_MCF52x2 Processor family CONFIG_MCF5253 MCF5253 specific CONFIG_M5253EVBE Amadeus Plus board specific - CFG_CLK Define Amadeus Plus CPU Clock - CFG_MBAR MBAR base address - CFG_MBAR2 MBAR2 base address + CONFIG_SYS_CLK Define Amadeus Plus CPU Clock + CONFIG_SYS_MBAR MBAR base address + CONFIG_SYS_MBAR2 MBAR2 base address 3.2 Compilation export CROSS_COMPILE=/usr/local/freescale-coldfire-4.1-elf/bin/m68k-elf- diff --git a/doc/README.m5373evb b/doc/README.m5373evb index b2ef4a5..4781d94 100644 --- a/doc/README.m5373evb +++ b/doc/README.m5373evb @@ -67,12 +67,12 @@ CONFIG_M5373 -- define for all Freescale MCF5373 CPUs CONFIG_M5373EVB -- define for M5373EVB board CONFIG_MCFUART -- define to use common CF Uart driver -CFG_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 CONFIG_BAUDRATE -- define UART baudrate CONFIG_MCFRTC -- define to use common CF RTC driver -CFG_MCFRTC_BASE -- provide base address for RTC in immap.h -CFG_RTC_OSCILLATOR -- define RTC clock frequency +CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h +CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency RTC_DEBUG -- define to show RTC debug message CONFIG_CMD_DATE -- enable to use date feature in u-boot @@ -80,11 +80,11 @@ CONFIG_MCFFEC -- define to use common CF FEC driver CONFIG_NET_MULTI -- define to use multi FEC in u-boot CONFIG_MII -- enable to use MII driver CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c -CFG_DISCOVER_PHY -- enable PHY discovery -CFG_RX_ETH_BUFFER -- Set FEC Receive buffer -CFG_FAULT_ECHO_LINK_DOWN-- -CFG_FEC0_PINMUX -- Set FEC0 Pin configuration -CFG_FEC0_MIIBASE -- Set FEC0 MII base register +CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery +CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer +CONFIG_SYS_FAULT_ECHO_LINK_DOWN-- +CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration +CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register MCFFEC_TOUT_LOOP -- set FEC timeout loop CONFIG_MCFTMR -- define to use DMA timer @@ -93,22 +93,22 @@ CONFIG_MCFPIT -- define to use PIT timer CONFIG_FSL_I2C -- define to use FSL common I2C driver CONFIG_HARD_I2C -- define for I2C hardware support CONFIG_SOFT_I2C -- define for I2C bit-banged -CFG_I2C_SPEED -- define for I2C speed -CFG_I2C_SLAVE -- define for I2C slave address -CFG_I2C_OFFSET -- define for I2C base address offset -CFG_IMMR -- define for MBAR offset +CONFIG_SYS_I2C_SPEED -- define for I2C speed +CONFIG_SYS_I2C_SLAVE -- define for I2C slave address +CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset +CONFIG_SYS_IMMR -- define for MBAR offset -CFG_MBAR -- define MBAR offset +CONFIG_SYS_MBAR -- define MBAR offset CONFIG_MONITOR_IS_IN_RAM -- Not support -CFG_INIT_RAM_ADDR -- defines the base address of the MCF5373 internal SRAM +CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5373 internal SRAM -CFG_CSn_BASE -- defines the Chip Select Base register -CFG_CSn_MASK -- defines the Chip Select Mask register -CFG_CSn_CTRL -- defines the Chip Select Control register +CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register +CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register +CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register -CFG_SDRAM_BASE -- defines the DRAM Base +CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base 2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL =========================================== diff --git a/doc/README.m54455evb b/doc/README.m54455evb index 5c01f0d..f695da5 100644 --- a/doc/README.m54455evb +++ b/doc/README.m54455evb @@ -71,12 +71,12 @@ CONFIG_M54455 -- define for all Freescale MCF54455 CPUs CONFIG_M54455EVB -- define for M54455EVB board CONFIG_MCFUART -- define to use common CF Uart driver -CFG_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 CONFIG_BAUDRATE -- define UART baudrate CONFIG_MCFRTC -- define to use common CF RTC driver -CFG_MCFRTC_BASE -- provide base address for RTC in immap.h -CFG_RTC_OSCILLATOR -- define RTC clock frequency +CONFIG_SYS_MCFRTC_BASE -- provide base address for RTC in immap.h +CONFIG_SYS_RTC_OSCILLATOR -- define RTC clock frequency RTC_DEBUG -- define to show RTC debug message CONFIG_CMD_DATE -- enable to use date feature in u-boot @@ -84,13 +84,13 @@ CONFIG_MCFFEC -- define to use common CF FEC driver CONFIG_NET_MULTI -- define to use multi FEC in u-boot CONFIG_MII -- enable to use MII driver CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c -CFG_DISCOVER_PHY -- enable PHY discovery -CFG_RX_ETH_BUFFER -- Set FEC Receive buffer -CFG_FAULT_ECHO_LINK_DOWN-- -CFG_FEC0_PINMUX -- Set FEC0 Pin configuration -CFG_FEC1_PINMUX -- Set FEC1 Pin configuration -CFG_FEC0_MIIBASE -- Set FEC0 MII base register -CFG_FEC1_MIIBASE -- Set FEC0 MII base register +CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery +CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer +CONFIG_SYS_FAULT_ECHO_LINK_DOWN-- +CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration +CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration +CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register +CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register MCFFEC_TOUT_LOOP -- set FEC timeout loop CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot @@ -100,14 +100,14 @@ CONFIG_IDE_RESET -- define ide_reset() CONFIG_IDE_PREINIT -- define ide_preinit() CONFIG_ATAPI -- define ATAPI support CONFIG_LBA48 -- define LBA48 (larger than 120GB) support -CFG_IDE_MAXBUS -- define max channel -CFG_IDE_MAXDEVICE -- define max devices per channel -CFG_ATA_BASE_ADDR -- define ATA base address -CFG_ATA_IDE0_OFFSET -- define ATA IDE0 offset -CFG_ATA_DATA_OFFSET -- define ATA data IO -CFG_ATA_REG_OFFSET -- define for normal register accesses -CFG_ATA_ALT_OFFSET -- define for alternate registers -CFG_ATA_STRIDE -- define for Interval between registers +CONFIG_SYS_IDE_MAXBUS -- define max channel +CONFIG_SYS_IDE_MAXDEVICE -- define max devices per channel +CONFIG_SYS_ATA_BASE_ADDR -- define ATA base address +CONFIG_SYS_ATA_IDE0_OFFSET -- define ATA IDE0 offset +CONFIG_SYS_ATA_DATA_OFFSET -- define ATA data IO +CONFIG_SYS_ATA_REG_OFFSET -- define for normal register accesses +CONFIG_SYS_ATA_ALT_OFFSET -- define for alternate registers +CONFIG_SYS_ATA_STRIDE -- define for Interval between registers _IO_BASE -- define for IO base address CONFIG_MCFTMR -- define to use DMA timer @@ -116,42 +116,42 @@ CONFIG_MCFPIT -- define to use PIT timer CONFIG_FSL_I2C -- define to use FSL common I2C driver CONFIG_HARD_I2C -- define for I2C hardware support CONFIG_SOFT_I2C -- define for I2C bit-banged -CFG_I2C_SPEED -- define for I2C speed -CFG_I2C_SLAVE -- define for I2C slave address -CFG_I2C_OFFSET -- define for I2C base address offset -CFG_IMMR -- define for MBAR offset +CONFIG_SYS_I2C_SPEED -- define for I2C speed +CONFIG_SYS_I2C_SLAVE -- define for I2C slave address +CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset +CONFIG_SYS_IMMR -- define for MBAR offset CONFIG_PCI -- define for PCI support CONFIG_PCI_PNP -- define for Plug n play support -CFG_PCI_MEM_BUS -- PCI memory logical offset -CFG_PCI_MEM_PHYS -- PCI memory physical offset -CFG_PCI_MEM_SIZE -- PCI memory size -CFG_PCI_IO_BUS -- PCI IO logical offset -CFG_PCI_IO_PHYS -- PCI IO physical offset -CFG_PCI_IO_SIZE -- PCI IO size -CFG_PCI_CFG_BUS -- PCI Configuration logical offset -CFG_PCI_CFG_PHYS -- PCI Configuration physical offset -CFG_PCI_CFG_SIZE -- PCI Configuration size +CONFIG_SYS_PCI_MEM_BUS -- PCI memory logical offset +CONFIG_SYS_PCI_MEM_PHYS -- PCI memory physical offset +CONFIG_SYS_PCI_MEM_SIZE -- PCI memory size +CONFIG_SYS_PCI_IO_BUS -- PCI IO logical offset +CONFIG_SYS_PCI_IO_PHYS -- PCI IO physical offset +CONFIG_SYS_PCI_IO_SIZE -- PCI IO size +CONFIG_SYS_PCI_CFG_BUS -- PCI Configuration logical offset +CONFIG_SYS_PCI_CFG_PHYS -- PCI Configuration physical offset +CONFIG_SYS_PCI_CFG_SIZE -- PCI Configuration size CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc -CFG_MBAR -- define MBAR offset +CONFIG_SYS_MBAR -- define MBAR offset -CFG_ATMEL_BOOT -- To determine the u-boot is booted from Atmel or Intel +CONFIG_SYS_ATMEL_BOOT -- To determine the u-boot is booted from Atmel or Intel CONFIG_MONITOR_IS_IN_RAM -- Not support -CFG_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM +CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM -CFG_CSn_BASE -- defines the Chip Select Base register -CFG_CSn_MASK -- defines the Chip Select Mask register -CFG_CSn_CTRL -- defines the Chip Select Control register +CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register +CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register +CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register -CFG_ATMEL_BASE -- defines the Atmel Flash base -CFG_INTEL_BASE -- defines the Intel Flash base +CONFIG_SYS_ATMEL_BASE -- defines the Atmel Flash base +CONFIG_SYS_INTEL_BASE -- defines the Intel Flash base -CFG_SDRAM_BASE -- defines the DRAM Base -CFG_SDRAM_BASE1 -- defines the DRAM Base 1 +CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base +CONFIG_SYS_SDRAM_BASE1 -- defines the DRAM Base 1 2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL =========================================== diff --git a/doc/README.m5475evb b/doc/README.m5475evb index 37d1438..dc9a605 100644 --- a/doc/README.m5475evb +++ b/doc/README.m5475evb @@ -74,20 +74,20 @@ CONFIG_M547x -- define for all Freescale MCF547x CPUs CONFIG_M5475 -- define for M5475EVB board CONFIG_MCFUART -- define to use common CF Uart driver -CFG_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 CONFIG_BAUDRATE -- define UART baudrate CONFIG_FSLDMAFEC -- define to use common dma FEC driver CONFIG_NET_MULTI -- define to use multi FEC in u-boot CONFIG_MII -- enable to use MII driver CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c -CFG_DISCOVER_PHY -- enable PHY discovery -CFG_RX_ETH_BUFFER -- Set FEC Receive buffer -CFG_FAULT_ECHO_LINK_DOWN-- -CFG_FEC0_PINMUX -- Set FEC0 Pin configuration -CFG_FEC1_PINMUX -- Set FEC1 Pin configuration -CFG_FEC0_MIIBASE -- Set FEC0 MII base register -CFG_FEC1_MIIBASE -- Set FEC0 MII base register +CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery +CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer +CONFIG_SYS_FAULT_ECHO_LINK_DOWN-- +CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration +CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration +CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register +CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register MCFFEC_TOUT_LOOP -- set FEC timeout loop CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot @@ -101,35 +101,35 @@ CONFIG_SLTTMR -- define to use SLT timer CONFIG_FSL_I2C -- define to use FSL common I2C driver CONFIG_HARD_I2C -- define for I2C hardware support CONFIG_SOFT_I2C -- define for I2C bit-banged -CFG_I2C_SPEED -- define for I2C speed -CFG_I2C_SLAVE -- define for I2C slave address -CFG_I2C_OFFSET -- define for I2C base address offset -CFG_IMMR -- define for MBAR offset +CONFIG_SYS_I2C_SPEED -- define for I2C speed +CONFIG_SYS_I2C_SLAVE -- define for I2C slave address +CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset +CONFIG_SYS_IMMR -- define for MBAR offset CONFIG_PCI -- define for PCI support CONFIG_PCI_PNP -- define for Plug n play support CONFIG_SKIPPCI_HOSTBRIDGE -- SKIP PCI Host bridge -CFG_PCI_MEM_BUS -- PCI memory logical offset -CFG_PCI_MEM_PHYS -- PCI memory physical offset -CFG_PCI_MEM_SIZE -- PCI memory size -CFG_PCI_IO_BUS -- PCI IO logical offset -CFG_PCI_IO_PHYS -- PCI IO physical offset -CFG_PCI_IO_SIZE -- PCI IO size -CFG_PCI_CFG_BUS -- PCI Configuration logical offset -CFG_PCI_CFG_PHYS -- PCI Configuration physical offset -CFG_PCI_CFG_SIZE -- PCI Configuration size +CONFIG_SYS_PCI_MEM_BUS -- PCI memory logical offset +CONFIG_SYS_PCI_MEM_PHYS -- PCI memory physical offset +CONFIG_SYS_PCI_MEM_SIZE -- PCI memory size +CONFIG_SYS_PCI_IO_BUS -- PCI IO logical offset +CONFIG_SYS_PCI_IO_PHYS -- PCI IO physical offset +CONFIG_SYS_PCI_IO_SIZE -- PCI IO size +CONFIG_SYS_PCI_CFG_BUS -- PCI Configuration logical offset +CONFIG_SYS_PCI_CFG_PHYS -- PCI Configuration physical offset +CONFIG_SYS_PCI_CFG_SIZE -- PCI Configuration size -CFG_MBAR -- define MBAR offset +CONFIG_SYS_MBAR -- define MBAR offset CONFIG_MONITOR_IS_IN_RAM -- Not support -CFG_INIT_RAM_ADDR -- defines the base address of the MCF547x internal SRAM +CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF547x internal SRAM -CFG_CSn_BASE -- defines the Chip Select Base register -CFG_CSn_MASK -- defines the Chip Select Mask register -CFG_CSn_CTRL -- defines the Chip Select Control register +CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register +CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register +CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register -CFG_SDRAM_BASE -- defines the DRAM Base +CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base 2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL =========================================== diff --git a/doc/README.m68k b/doc/README.m68k index 0c533f3..e6c33a7 100644 --- a/doc/README.m68k +++ b/doc/README.m68k @@ -72,7 +72,7 @@ For the preloader, please see http://mailman.uclinux.org/pipermail/uclinux-dev/2003-December/023384.html U-boot is configured to run at 0x20000 at default. This can be configured by -change TEXT_BASE in board/m5282evb/config.mk and CFG_MONITOR_BASE in +change TEXT_BASE in board/m5282evb/config.mk and CONFIG_SYS_MONITOR_BASE in include/configs/M5282EVB.h. 3.2 BuS EB+MCF-EV123 @@ -95,7 +95,7 @@ If u-boot should be loaded to RAM and started by a pre-loader CONFIG_MONITOR_IS_IN_RAM must be defined. If it is defined the initial vector table and basic processor initialization will not be compiled in. The start address of u-boot must be adjusted in -the boards config header file (CFG_MONITOR_BASE) and Makefile +the boards config header file (CONFIG_SYS_MONITOR_BASE) and Makefile (TEXT_BASE) to the load address. 4.1 MCF5272 specific Options/Settings @@ -107,20 +107,20 @@ CONFIG_M5272 -- defined for all Motorola MCF5272 CPUs CONFIG_MONITOR_IS_IN_RAM -- defined if u-boot is loaded by a pre-loader -CFG_MBAR -- defines the base address of the MCF5272 configuration registers -CFG_INIT_RAM_ADDR +CONFIG_SYS_MBAR -- defines the base address of the MCF5272 configuration registers +CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5272 internal SRAM -CFG_ENET_BD_BASE +CONFIG_SYS_ENET_BD_BASE -- defines the base addres of the FEC buffer descriptors -CFG_SCR -- defines the contents of the System Configuration Register -CFG_SPR -- defines the contents of the System Protection Register -CFG_BRx_PRELIM -- defines the contents of the Chip Select Base Registers -CFG_ORx_PRELIM -- defines the contents of the Chip Select Option Registers +CONFIG_SYS_SCR -- defines the contents of the System Configuration Register +CONFIG_SYS_SPR -- defines the contents of the System Protection Register +CONFIG_SYS_BRx_PRELIM -- defines the contents of the Chip Select Base Registers +CONFIG_SYS_ORx_PRELIM -- defines the contents of the Chip Select Option Registers -CFG_PxDDR -- defines the contents of the Data Direction Registers -CFG_PxDAT -- defines the contents of the Data Registers -CFG_PXCNT -- defines the contents of the Port Configuration Registers +CONFIG_SYS_PxDDR -- defines the contents of the Data Direction Registers +CONFIG_SYS_PxDAT -- defines the contents of the Data Registers +CONFIG_SYS_PXCNT -- defines the contents of the Port Configuration Registers 4.2 MCF5282 specific Options/Settings @@ -132,32 +132,32 @@ CONFIG_M5282 -- defined for all Motorola MCF5282 CPUs CONFIG_MONITOR_IS_IN_RAM -- defined if u-boot is loaded by a pre-loader -CFG_MBAR -- defines the base address of the MCF5282 internal register space -CFG_INIT_RAM_ADDR +CONFIG_SYS_MBAR -- defines the base address of the MCF5282 internal register space +CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5282 internal SRAM -CFG_INT_FLASH_BASE +CONFIG_SYS_INT_FLASH_BASE -- defines the base address of the MCF5282 internal Flash memory -CFG_ENET_BD_BASE +CONFIG_SYS_ENET_BD_BASE -- defines the base addres of the FEC buffer descriptors -CFG_MFD +CONFIG_SYS_MFD -- defines the PLL Multiplication Factor Devider (see table 9-4 of MCF user manual) -CFG_RFD -- defines the PLL Reduce Frecuency Devider +CONFIG_SYS_RFD -- defines the PLL Reduce Frecuency Devider (see table 9-4 of MCF user manual) -CFG_CSx_BASE -- defines the base address of chip select x -CFG_CSx_SIZE -- defines the memory size (address range) of chip select x -CFG_CSx_WIDTH -- defines the bus with of chip select x -CFG_CSx_RO -- if set to 0 chip select x is read/wirte +CONFIG_SYS_CSx_BASE -- defines the base address of chip select x +CONFIG_SYS_CSx_SIZE -- defines the memory size (address range) of chip select x +CONFIG_SYS_CSx_WIDTH -- defines the bus with of chip select x +CONFIG_SYS_CSx_RO -- if set to 0 chip select x is read/wirte else chipselct is read only -CFG_CSx_WS -- defines the number of wait states of chip select x +CONFIG_SYS_CSx_WS -- defines the number of wait states of chip select x -CFG_PxDDR -- defines the contents of the Data Direction Registers -CFG_PxDAT -- defines the contents of the Data Registers -CFG_PXCNT -- defines the contents of the Port Configuration Registers +CONFIG_SYS_PxDDR -- defines the contents of the Data Direction Registers +CONFIG_SYS_PxDAT -- defines the contents of the Data Registers +CONFIG_SYS_PXCNT -- defines the contents of the Port Configuration Registers -CFG_PxPAR -- defines the function of ports +CONFIG_SYS_PxPAR -- defines the function of ports 5. COMPILER diff --git a/doc/README.marubun-pcmcia b/doc/README.marubun-pcmcia index 6099da2..d3563a3 100644 --- a/doc/README.marubun-pcmcia +++ b/doc/README.marubun-pcmcia @@ -33,28 +33,28 @@ U-Boot MARUBUN MR-SHPC-01 PCMCIA controller driver Most devices have only one slot. You should define CONFIG_PCMCIA_SLOT_A . ex. #define CONFIG_PCMCIA_SLOT_A 1 - * CFG_MARUBUN_MRSHPC + * CONFIG_SYS_MARUBUN_MRSHPC This is MR-SHPC-01 PCMCIA controler base address. You should do the setting matched to your environment. - ex. #define CFG_MARUBUN_MRSHPC 0xb03fffe0 + ex. #define CONFIG_SYS_MARUBUN_MRSHPC 0xb03fffe0 ( for MS7722SE01 environment ) - * CFG_MARUBUN_MW1 + * CONFIG_SYS_MARUBUN_MW1 This is MR-SHPC-01 memory window base address. You should do the setting matched to your environment. - ex. #define CFG_MARUBUN_MW1 0xb0400000 + ex. #define CONFIG_SYS_MARUBUN_MW1 0xb0400000 ( for MS7722SE01 environment ) - * CFG_MARUBUN_MW1 + * CONFIG_SYS_MARUBUN_MW1 This is MR-SHPC-01 attribute window base address. You should do the setting matched to your environment. - ex. #define CFG_MARUBUN_MW2 0xb0500000 + ex. #define CONFIG_SYS_MARUBUN_MW2 0xb0500000 ( for MS7722SE01 environment ) - * CFG_MARUBUN_MW1 + * CONFIG_SYS_MARUBUN_MW1 This is MR-SHPC-01 I/O window base address. You should do the setting matched to your environment. - ex. #define CFG_MARUBUN_IO 0xb0600000 + ex. #define CONFIG_SYS_MARUBUN_IO 0xb0600000 ( for MS7722SE01 environment ) 3. Other diff --git a/doc/README.mpc8313erdb b/doc/README.mpc8313erdb index cd56689..7c1af17 100644 --- a/doc/README.mpc8313erdb +++ b/doc/README.mpc8313erdb @@ -3,7 +3,7 @@ Freescale MPC8313ERDB Board 1. Board Switches and Jumpers - S3 is used to set CFG_RESET_SOURCE. + S3 is used to set CONFIG_SYS_RESET_SOURCE. To boot the image at 0xFE000000 in NOR flash, use these DIP switch settings for S3 S4: diff --git a/doc/README.mpc8315erdb b/doc/README.mpc8315erdb index e77eba7..7d476d0 100644 --- a/doc/README.mpc8315erdb +++ b/doc/README.mpc8315erdb @@ -3,7 +3,7 @@ Freescale MPC8315ERDB Board 1. Board Switches and Jumpers - S3 is used to set CFG_RESET_SOURCE. + S3 is used to set CONFIG_SYS_RESET_SOURCE. To boot the image at 0xFE000000 in NOR flash, use these DIP switch settings for S3 S4: diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn index 1c41d77..2c3c703 100644 --- a/doc/README.mpc8641hpcn +++ b/doc/README.mpc8641hpcn @@ -21,16 +21,16 @@ Jumpers: J14 Pins 1-2 (near plcc32 socket) Switches: - SW1(1-5) = 01100 CFG_COREPLL = 01000 :: CORE = 2:1 + SW1(1-5) = 01100 CONFIG_SYS_COREPLL = 01000 :: CORE = 2:1 01100 :: CORE = 2.5:1 10000 :: CORE = 3:1 11100 :: CORE = 3.5:1 10100 :: CORE = 4:1 01110 :: CORE = 4.5:1 - SW1(6-8) = 001 CFG_SYSCLK = 000 :: SYSCLK = 33MHz + SW1(6-8) = 001 CONFIG_SYS_SYSCLK = 000 :: SYSCLK = 33MHz 001 :: SYSCLK = 40MHz - SW2(1-4) = 1100 CFG_CCBPLL = 0010 :: 2X + SW2(1-4) = 1100 CONFIG_SYS_CCBPLL = 0010 :: 2X 0100 :: 4X 0110 :: 6X 1000 :: 8X @@ -38,34 +38,34 @@ Switches: 1100 :: 12X 1110 :: 14X 0000 :: 16X - SW2(5-8) = 1110 CFG_BOOTLOC = 1110 :: boot 16-bit localbus + SW2(5-8) = 1110 CONFIG_SYS_BOOTLOC = 1110 :: boot 16-bit localbus - SW3(1-7) = 0011000 CFG_VID = 0011000 :: VCORE = 1.2V + SW3(1-7) = 0011000 CONFIG_SYS_VID = 0011000 :: VCORE = 1.2V 0100000 :: VCORE = 1.11V SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V 1 :: VCC_PLAT = 1.0V - SW4(1-2) = 11 CFG_HOSTMODE = 11 :: both prots host/root - SW4(3-4) = 11 CFG_BOOTSEQ = 11 :: no boot seq - SW4(5-8) = 0011 CFG_IOPORT = 0011 :: both PEX + SW4(1-2) = 11 CONFIG_SYS_HOSTMODE = 11 :: both prots host/root + SW4(3-4) = 11 CONFIG_SYS_BOOTSEQ = 11 :: no boot seq + SW4(5-8) = 0011 CONFIG_SYS_IOPORT = 0011 :: both PEX - SW5(1) = 1 CFG_FLASHMAP = 1 :: boot from flash + SW5(1) = 1 CONFIG_SYS_FLASHMAP = 1 :: boot from flash 0 :: boot from PromJet - SW5(2) = 1 CFG_FLASHBANK = 1 :: swap upper/lower + SW5(2) = 1 CONFIG_SYS_FLASHBANK = 1 :: swap upper/lower halves (virtual banks) 0 :: normal - SW5(3) = 0 CFG_FLASHWP = 0 :: not protected - SW5(4) = 0 CFG_PORTDIV = 1 :: 2:1 for PD4 + SW5(3) = 0 CONFIG_SYS_FLASHWP = 0 :: not protected + SW5(4) = 0 CONFIG_SYS_PORTDIV = 1 :: 2:1 for PD4 1:1 for PD6 - SW5(5-6) = 11 CFG_PIXISOPT = 11 :: s/w determined - SW5(7-8) = 11 CFG_LADOPT = 11 :: s/w determined + SW5(5-6) = 11 CONFIG_SYS_PIXISOPT = 11 :: s/w determined + SW5(7-8) = 11 CONFIG_SYS_LADOPT = 11 :: s/w determined - SW6(1) = 1 CFG_CPUBOOT = 1 :: no boot holdoff - SW6(2) = 1 CFG_BOOTADDR = 1 :: no traslation - SW6(3-5) = 000 CFG_REFCLKSEL = 000 :: 100MHZ - SW6(6) = 1 CFG_SERROM_ADDR= 1 :: - SW6(7) = 1 CFG_MEMDEBUG = 1 :: - SW6(8) = 1 CFG_DDRDEBUG = 1 :: + SW6(1) = 1 CONFIG_SYS_CPUBOOT = 1 :: no boot holdoff + SW6(2) = 1 CONFIG_SYS_BOOTADDR = 1 :: no traslation + SW6(3-5) = 000 CONFIG_SYS_REFCLKSEL = 000 :: 100MHZ + SW6(6) = 1 CONFIG_SYS_SERROM_ADDR= 1 :: + SW6(7) = 1 CONFIG_SYS_MEMDEBUG = 1 :: + SW6(8) = 1 CONFIG_SYS_DDRDEBUG = 1 :: SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49 SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled @@ -74,7 +74,7 @@ Switches: SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled SW8(7) = 1 ACPWR = 1 :: non-battery - SW8(8) = 0 CFG_IDWP = 0 :: write enable + SW8(8) = 0 CONFIG_SYS_IDWP = 0 :: write enable 3. Flash U-Boot diff --git a/doc/README.nand b/doc/README.nand index 6dac24c..bf80bc0 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -95,7 +95,7 @@ Configuration Options: CONFIG_MTD_NAND_ECC_YAFFS would be another useful choice for someone to implement. - CFG_MAX_NAND_DEVICE + CONFIG_SYS_MAX_NAND_DEVICE The maximum number of NAND devices you want to support. NAND Interface: @@ -164,7 +164,7 @@ More Definitions: These definitions are needed in the board configuration for now, but may really belong in a header file. TODO: Figure which ones are truly configuration settings and rename - them to CFG_NAND_... and move the rest somewhere appropriate. + them to CONFIG_SYS_NAND_... and move the rest somewhere appropriate. #define SECTORSIZE 512 #define ADDR_COLUMN 1 @@ -174,7 +174,7 @@ More Definitions: #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 - #define CFG_DAVINCI_BROKEN_ECC + #define CONFIG_SYS_DAVINCI_BROKEN_ECC Versions of U-Boot <= 1.3.3 and Montavista Linux kernels generated bogus ECCs on large-page NAND. Both large and small page NAND ECCs were incompatible with the Linux davinci git tree (since diff --git a/doc/README.nios b/doc/README.nios index 2f11489..7f34938 100644 --- a/doc/README.nios +++ b/doc/README.nios @@ -68,11 +68,11 @@ port are not currently implemented. 2.1 Nios-specific Options/Settings ----------------------------------- All configuration options/settings that are specific to Nios begin -with "CONFIG_NIOS_", "CFG_NIOS_", or "CFG_NIOS_CPU_". +with "CONFIG_NIOS_", "CONFIG_SYS_NIOS_", or "CONFIG_SYS_NIOS_CPU_". The configuration follows a two-stage process. In the first stage the NIOS CPU core will defined like defined in Alteras SOPC Builder. -At this point we use the "CFG_NIOS_CPU_" defines exclusively. For +At this point we use the "CONFIG_SYS_NIOS_CPU_" defines exclusively. For more informations about all the definitions you have to setup see into current board configurations and doc/README.nios_CFG_NIOS_CPU. @@ -85,41 +85,41 @@ description). CONFIG_NIOS -- defined for all Nios-32 boards. -CFG_NIOS_CONSOLE -- the base address of the console UART or the JTAG +CONFIG_SYS_NIOS_CONSOLE -- the base address of the console UART or the JTAG stdio port. To enable a console via JTAG, define CONFIG_CONSOLE_JTAG and set CGF_NIOS_CONSOLE to the base address of the JTAG stdio port (normally OCI base + 0x00fa). Then run nios-console with the -w option. (standard-32: nasys_uart_0 resp. na_uart1_base). -CFG_NIOS_FIXEDBAUD -- defined if the console UART PTF fixed_baud +CONFIG_SYS_NIOS_FIXEDBAUD -- defined if the console UART PTF fixed_baud parameter is set to '1'. -CFG_NIOS_MULT_HW -- use full hardware multiply (not yet implemented). +CONFIG_SYS_NIOS_MULT_HW -- use full hardware multiply (not yet implemented). -CFG_NIOS_MULT_MSTEP -- use hardware assisted multiply using the +CONFIG_SYS_NIOS_MULT_MSTEP -- use hardware assisted multiply using the MSTEP instruction (not yet implemented). -CFG_NIOS_TMRBASE -- the base address of the timer used to support +CONFIG_SYS_NIOS_TMRBASE -- the base address of the timer used to support xxx_timer routines (e.g. set_timer(), get_timer(), etc.). (standard-32: nasys_timer_1 resp. na_lo_priority_timer2_base). -CFG_NIOS_TMRIRQ -- the interrupt request (vector number) assigned to +CONFIG_SYS_NIOS_TMRIRQ -- the interrupt request (vector number) assigned to the timer. (standard-32: nasys_timer_1_irq resp. na_low_priority_timer2_irq). -CFG_NIOS_TMRMS -- the period of the timer in milliseconds. +CONFIG_SYS_NIOS_TMRMS -- the period of the timer in milliseconds. -CFG_NIOS_TMRCNT -- the preloadable counter value for the timer if it has +CONFIG_SYS_NIOS_TMRCNT -- the preloadable counter value for the timer if it has no fixed period. -CFG_NIOS_ASMIBASE -- the base address of the ASMI peripheral. +CONFIG_SYS_NIOS_ASMIBASE -- the base address of the ASMI peripheral. (standard-32: na_asmi_base). -CFG_NIOS_SPIBASE -- the base address of the SPI master (!) peripheral. +CONFIG_SYS_NIOS_SPIBASE -- the base address of the SPI master (!) peripheral. (nasys_spi_0) -CFG_NIOS_SPIBITS -- the amount of configured SPI data bits in PTF. +CONFIG_SYS_NIOS_SPIBITS -- the amount of configured SPI data bits in PTF. This value can be 8 or 16 only! (PTF: databits) @@ -128,7 +128,7 @@ CFG_NIOS_SPIBITS -- the amount of configured SPI data bits in PTF. Some 'standard' U-Boot options/settings are treated differently in the Nios port. These are described below. -CFG_GBL_DATA_OFFSET -- in the Nios port, this is the offset of the +CONFIG_SYS_GBL_DATA_OFFSET -- in the Nios port, this is the offset of the global data structure in the Nios memory space. More simply, the address of global data. @@ -156,17 +156,17 @@ but does not appear in the programmer's manual. 4.1 Boot process over GERMS --------------------------- When the NIOS CPU catch a reset signal it will begin to be running -code from CFG_NIOS_CPU_RST_VECT. Normally at this place it will +code from CONFIG_SYS_NIOS_CPU_RST_VECT. Normally at this place it will find the GERMS monitor. That's the case for the generic NIOS CPU configuration "standard_32". When the GERMS monitor starts running, it performs important system initializations and then looks for executable code in flash, using the following steps: - 1. Examining the two bytes at CFG_NIOS_CPU_FLASH_BASE + 0x04000C. - 2. Examining the button 0 on the PIO CFG_NIOS_CPU_BUTTON_PIO. + 1. Examining the two bytes at CONFIG_SYS_NIOS_CPU_FLASH_BASE + 0x04000C. + 2. Examining the button 0 on the PIO CONFIG_SYS_NIOS_CPU_BUTTON_PIO. 3. If the button is not pressed and the two bytes contain 'N' and 'i', the monitor executes a CALL to location - CFG_NIOS_CPU_FLASH_BASE + 0x040000. + CONFIG_SYS_NIOS_CPU_FLASH_BASE + 0x040000. 4. If the code is not executed in step 3 or the code returns, then prints an 8-digit version number to STDOUT and waits for user commands from STDIN. @@ -181,9 +181,9 @@ of application software in flash memory. If found, the processor immediately executes the code. To return program execution to the GERMS monitor (that is, avoid running code stored in flash memory): - 1. Hold down CFG_NIOS_CPU_BUTTON_PIO, button number 0. + 1. Hold down CONFIG_SYS_NIOS_CPU_BUTTON_PIO, button number 0. 2. Press then release the CPU reset button. - 3. Release CFG_NIOS_CPU_BUTTON_PIO, button number 0. + 3. Release CONFIG_SYS_NIOS_CPU_BUTTON_PIO, button number 0. 5. DEBUGGING WITH GDB @@ -354,7 +354,7 @@ for those interested in contributing: -Add boot support for ucLinux (niosnommu). -Implement (don't copy Altera code) the __mulxx routines using the - MSTEP and MUL instructions (e.g. CFG_NIOS_MULT_HW and CFG_NIOS_MULT_MSTEP). + MSTEP and MUL instructions (e.g. CONFIG_SYS_NIOS_MULT_HW and CONFIG_SYS_NIOS_MULT_MSTEP). Regards, diff --git a/doc/README.nios_CFG_NIOS_CPU b/doc/README.nios_CFG_NIOS_CPU deleted file mode 100644 index e38ed91..0000000 --- a/doc/README.nios_CFG_NIOS_CPU +++ /dev/null @@ -1,140 +0,0 @@ - -=============================================================================== - C F G _ N I O S _ C P U _ * v s . N I O S S D K -=============================================================================== - -When ever you have to make a new NIOS CPU configuration you can use this table -as a reference list to the original NIOS SDK symbols made by Alteras SOPC -Builder. Look into excalibur.h and excalibur.s in your SDK path cpu_sdk/inc. -Symbols beginning with a '[ptf]:' are coming from your SOPC sytem description -(PTF file) in sections WIZARD_SCRIPT_ARGUMENTS or SYSTEM_BUILDER_INFO. - -C O R E N I O S S D K [1],[7] -------------------------------------------------------------------------------- -CFG_NIOS_CPU_CLK nasys_clock_freq -CFG_NIOS_CPU_ICACHE nasys_icache_size -CFG_NIOS_CPU_DCACHE nasys_dcache_size -CFG_NIOS_CPU_REG_NUMS nasys_nios_num_regs -CFG_NIOS_CPU_MUL __nios_use_multiply__ -CFG_NIOS_CPU_MSTEP __nios_use_mstep__ -CFG_NIOS_CPU_STACK nasys_stack_top -CFG_NIOS_CPU_VEC_BASE nasys_vector_table -CFG_NIOS_CPU_VEC_SIZE nasys_vector_table_size -CFG_NIOS_CPU_VEC_NUMS -CFG_NIOS_CPU_RST_VECT nasys_reset_address -CFG_NIOS_CPU_DBG_CORE nasys_debug_core -CFG_NIOS_CPU_RAM_BASE na_onchip_ram_64_kbytes -CFG_NIOS_CPU_RAM_SIZE na_onchip_ram_64_kbytes_size -CFG_NIOS_CPU_ROM_BASE na_boot_monitor_rom -CFG_NIOS_CPU_ROM_SIZE na_boot_monitor_rom_size -CFG_NIOS_CPU_OCI_BASE nasys_oci_core -CFG_NIOS_CPU_OCI_SIZE -CFG_NIOS_CPU_SRAM_BASE na_ext_ram nasys_program_mem - nasys_data_mem -CFG_NIOS_CPU_SRAM_SIZE na_ext_ram_size nasys_program_mem_size - nasys_data_mem_size -CFG_NIOS_CPU_SDRAM_BASE na_sdram -CFG_NIOS_CPU_SDRAM_SIZE na_sdram_size -CFG_NIOS_CPU_FLASH_BASE na_ext_flash nasys_main_flash - nasys_am29lv065d_flash_0 - nasys_flash_0 -CFG_NIOS_CPU_FLASH_SIZE na_ext_flash_size nasys_main_flash_size - -T I M E R N I O S S D K [3] -------------------------------------------------------------------------------- -CFG_NIOS_CPU_TIMER_NUMS nasys_timer_count -CFG_NIOS_CPU_TIMER[0-9] nasys_timer_[0-9] -CFG_NIOS_CPU_TIMER[0-9]_IRQ nasys_timer_[0-9]_irq -CFG_NIOS_CPU_TIMER[0-9]_PER [ptf]:period - [ptf]:period_units - [ptf]:mult -CFG_NIOS_CPU_TIMER[0-9]_AR [ptf]:always_run -CFG_NIOS_CPU_TIMER[0-9]_FP [ptf]:fixed_period -CFG_NIOS_CPU_TIMER[0-9]_SS [ptf]:snapshot - -U A R T N I O S S D K [2] -------------------------------------------------------------------------------- -CFG_NIOS_CPU_UART_NUMS nasys_uart_count -CFG_NIOS_CPU_UART[0-9] nasys_uart_[0-9] -CFG_NIOS_CPU_UART[0-9]_IRQ nasys_uart_[0-9]_irq -CFG_NIOS_CPU_UART[0-9]_BR [ptf]:baud -CFG_NIOS_CPU_UART[0-9]_DB [ptf]:data_bits -CFG_NIOS_CPU_UART[0-9]_SB [ptf]:stop_bits -CFG_NIOS_CPU_UART[0-9]_PA [ptf]:parity -CFG_NIOS_CPU_UART[0-9]_HS [ptf]:use_cts_rts -CFG_NIOS_CPU_UART[0-9]_EOP [ptf]:use_eop_register - -P I O N I O S S D K [4] -------------------------------------------------------------------------------- -CFG_NIOS_CPU_PIO_NUMS nasys_pio_count -CFG_NIOS_CPU_PIO[0-9] nasys_pio_[0-9] -CFG_NIOS_CPU_PIO[0-9]_IRQ nasys_pio_[0-9]_irq -CFG_NIOS_CPU_PIO[0-9]_BITS [ptf]:Data_Width -CFG_NIOS_CPU_PIO[0-9]_TYPE [ptf]:has_tri - [ptf]:has_out - [ptf]:has_in -CFG_NIOS_CPU_PIO[0-9]_CAP [ptf]:capture -CFG_NIOS_CPU_PIO[0-9]_EDGE [ptf]:edge_type -CFG_NIOS_CPU_PIO[0-9]_ITYPE [ptf]:irq_type - -S P I N I O S S D K [6] -------------------------------------------------------------------------------- -CFG_NIOS_CPU_SPI_NUMS nasys_spi_count -CFG_NIOS_CPU_SPI[0-9] nasys_spi_[0-9] -CFG_NIOS_CPU_SPI[0-9]_IRQ nasys_spi_[0-9]_irq -CFG_NIOS_CPU_SPI[0-9]_BITS [ptf]:databits -CFG_NIOS_CPU_SPI[0-9]_MA [ptf]:ismaster -CFG_NIOS_CPU_SPI[0-9]_SLN [ptf]:numslaves -CFG_NIOS_CPU_SPI[0-9]_TCLK [ptf]:targetclock -CFG_NIOS_CPU_SPI[0-9]_TDELAY [ptf]:targetdelay -CFG_NIOS_CPU_SPI[0-9]_* [ptf]:* - -I D E N I O S S D K -------------------------------------------------------------------------------- -CFG_NIOS_CPU_IDE_NUMS nasys_usersocket_count -CFG_NIOS_CPU_IDE[0-9] nasys_usersocket_[0-9] - -A S M I N I O S S D K [5] -------------------------------------------------------------------------------- -CFG_NIOS_CPU_ASMI_NUMS nasys_asmi_count -CFG_NIOS_CPU_ASMI[0-9] nasys_asmi_[0-9] -CFG_NIOS_CPU_ASMI[0-9]_IRQ nasys_asmi_[0-9]_irq - -E t h e r n e t ( L A N ) N I O S S D K -------------------------------------------------------------------------------- -CFG_NIOS_CPU_LAN_NUMS -CFG_NIOS_CPU_LAN[0-9]_BASE na_lan91c111 -CFG_NIOS_CPU_LAN[0-9]_OFFS LAN91C111_REGISTERS_OFFSET -CFG_NIOS_CPU_LAN[0-9]_IRQ na_lan91c111_irq -CFG_NIOS_CPU_LAN[0-9]_BUSW LAN91C111_DATA_BUS_WIDTH -CFG_NIOS_CPU_LAN[0-9]_TYPE - -s y s t e m c o m p o s i n g N I O S S D K -------------------------------------------------------------------------------- -CFG_NIOS_CPU_TICK_TIMER (na_low_priority_timer2) -CFG_NIOS_CPU_USER_TIMER (na_timer1) -CFG_NIOS_CPU_BUTTON_PIO (na_button_pio) -CFG_NIOS_CPU_LCD_PIO (na_lcd_pio) -CFG_NIOS_CPU_LED_PIO (na_led_pio) -CFG_NIOS_CPU_SEVENSEG_PIO (na_seven_seg_pio) -CFG_NIOS_CPU_RECONF_PIO (na_reconfig_request_pio) -CFG_NIOS_CPU_CFPRESENT_PIO (na_cf_present_pio) -CFG_NIOS_CPU_CFPOWER_PIO (na_cf_power_pio) -CFG_NIOS_CPU_CFATASEL_PIO (na_cf_ata_select_pio) -CFG_NIOS_CPU_USER_SPI (na_spi) - - -=============================================================================== - R E F E R E N C E S -=============================================================================== -[1] http://www.altera.com/literature/ds/ds_nioscpu.pdf -[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf -[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf -[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf -[5] http://www.altera.com/literature/ds/ds_nios_asmi.pdf -[6] http://www.altera.com/literature/ds/ds_nios_spi.pdf -[7] http://www.altera.com/literature/ds/ds_legacy_sdram_ctrl.pdf - - -=============================================================================== -Stephan Linz <linz@li-pro.net> diff --git a/doc/README.ppc440 b/doc/README.ppc440 index 2e04aba..0a5f99f 100644 --- a/doc/README.ppc440 +++ b/doc/README.ppc440 @@ -47,25 +47,25 @@ the cpu-specific code (vs. board-specific code), so you should at least review these before deciding to make any changes ... it will probably save you some headaches ;-) -CFG_SDRAM_BASE - The virtual address where SDRAM is mapped (always 0) +CONFIG_SYS_SDRAM_BASE - The virtual address where SDRAM is mapped (always 0) -CFG_FLASH_BASE - The virtual address where FLASH is mapped. +CONFIG_SYS_FLASH_BASE - The virtual address where FLASH is mapped. -CFG_PCI_MEMBASE - The virtual address where PCI-bus memory is mapped. +CONFIG_SYS_PCI_MEMBASE - The virtual address where PCI-bus memory is mapped. This mapping provides access to PCI-bus memory. -CFG_PERIPHERAL_BASE - The virtual address where the 440 memory-mapped +CONFIG_SYS_PERIPHERAL_BASE - The virtual address where the 440 memory-mapped peripherals are mapped. (e.g. -- UART registers, IIC registers, etc). -CFG_ISRAM_BASE - The virtual address where the 440 internal SRAM is +CONFIG_SYS_ISRAM_BASE - The virtual address where the 440 internal SRAM is mapped. The internal SRAM is equivalent to 405gp OCM and is used for the initial stack. -CFG_PCI_BASE - The virtual address where the 440 PCI-x bridge config +CONFIG_SYS_PCI_BASE - The virtual address where the 440 PCI-x bridge config registers are mapped. -CFG_PCI_TARGBASE - The PCI address that is mapped to the virtual address - defined by CFG_PCI_MEMBASE. +CONFIG_SYS_PCI_TARGBASE - The PCI address that is mapped to the virtual address + defined by CONFIG_SYS_PCI_MEMBASE. UART / SERIAL @@ -73,7 +73,7 @@ UART / SERIAL The UART port works fine when an external serial clock is provided (like the one on the Ebony board) and when using internal clocking. -This is controlled with the CFG_EXT_SERIAL_CLOCK flag. When using +This is controlled with the CONFIG_SYS_EXT_SERIAL_CLOCK flag. When using internal clocking, the "ideal baud rate" settings in the 440GP user manual are automatically calculated. @@ -94,7 +94,7 @@ cause problems when a probe (read) is performed (for example the CDCV850 clock controller at address 0x69 on the ebony board). To prevent probing certain addresses you can define the -CFG_I2C_NOPROBES macro in your board-specific header file. When +CONFIG_SYS_I2C_NOPROBES macro in your board-specific header file. When defined, all specified addresses are skipped during a probe. The addresses that are skipped will be displayed in the output of the iprobe command. @@ -102,12 +102,12 @@ of the iprobe command. For example, to prevent probing address 0x69, define the macro as follows: -#define CFG_I2C_NOPROBES {0x69} +#define CONFIG_SYS_I2C_NOPROBES {0x69} Similarly, to prevent probing addresses 0x69 and 0x70, define the macro a: -#define CFG_I2C_NOPROBES {0x69, 0x70} +#define CONFIG_SYS_I2C_NOPROBES {0x69, 0x70} DDR SDRAM CONTROLLER @@ -144,7 +144,7 @@ utilities once you get to the U-Boot command prompt. NOTE: the default The cpu-specific code sets up a default pci_controller structure that maps in a single PCI I/O space and PCI memory space. The I/O space begins at PCI I/O address 0 and the PCI memory space is -256 MB starting at PCI address CFG_PCI_TARGBASE. After the +256 MB starting at PCI address CONFIG_SYS_PCI_TARGBASE. After the pci_controller structure is initialized, the cpu-specific code will call the routine pci_pre_init(). This routine is implemented by board-specific code & is where the board can over-ride/extend the @@ -157,7 +157,7 @@ initialization continues. The default 440GP PCI target configuration is minimal -- it assumes that the strapping registers are set as necessary. Since the strapping bits provide very limited flexibility, you may want to customize the boards -target configuration. If CFG_PCI_TARGET_INIT is defined, the cpu-specific +target configuration. If CONFIG_SYS_PCI_TARGET_INIT is defined, the cpu-specific code will call the routine pci_target_init() which you must implement in your board-specific code. @@ -166,7 +166,7 @@ initializing the subsystem id and subsystem vendor id, and then ensuring that the 'enable host configuration' bit in the PCIX0_BRDGOPT2 is set. The default PCI master initialization maps in 256 MB of pci memory -starting at PCI address CFG_PCI_MEMBASE. To customize this, define +starting at PCI address CONFIG_SYS_PCI_MEMBASE. To customize this, define PCI_MASTER_INIT. This will call the routine pci_master_init() in your board-specific code rather than performing the default master initialization. diff --git a/doc/README.serial_multi b/doc/README.serial_multi index 40f7815..ad61d42 100644 --- a/doc/README.serial_multi +++ b/doc/README.serial_multi @@ -35,7 +35,7 @@ just after switching the console: setenv sout serial_scc; setenv baudrate 38400 After that press 'enter' at the SCC console. Note that baudrates <38400 -are not allowed on LWMON with watchdog enabled (see CFG_BAUDRATE_TABLE in +are not allowed on LWMON with watchdog enabled (see CONFIG_SYS_BAUDRATE_TABLE in include/configs/lwmon.h). diff --git a/doc/README.sha1 b/doc/README.sha1 index 7992f7f..f6cca40 100644 --- a/doc/README.sha1 +++ b/doc/README.sha1 @@ -34,7 +34,7 @@ a) cp the new Image on a position in RAM (here 0x300000) b) Initialize the SHA1 sum in the Image with 0x00 The SHA1 sum is stored in Flash at: - CFG_MONITOR_BASE + CFG_MONITOR_LEN + SHA1_SUM_POS + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + SHA1_SUM_POS for the pcs440ep Flash: 0xfffa0000 + 0x60000 + -0x20 = 0xffffffe0 for the example in RAM: 0x300000 + 0x60000 + -0x20 diff --git a/doc/README.silent b/doc/README.silent index 6772532..a26e3df 100644 --- a/doc/README.silent +++ b/doc/README.silent @@ -13,7 +13,7 @@ The following actions are taken if "silent" is set at boot time: - When the console devices have been initialized, "stdout" and "stderr" are set to "nulldev", so subsequent messages are suppressed automatically. Make sure to enable "nulldev" by - #defining CFG_DEVICE_NULLDEV in your board config file. + #defining CONFIG_SYS_DEVICE_NULLDEV in your board config file. - When booting a linux kernel, the "bootargs" are fixed up so that the argument "console=" will be in the command line, no matter how diff --git a/doc/README.update b/doc/README.update new file mode 100644 index 0000000..a476002 --- /dev/null +++ b/doc/README.update @@ -0,0 +1,90 @@ +Automatic software update from a TFTP server +============================================ + +Overview +-------- + +This feature allows to automatically store software updates present on a TFTP +server in NOR Flash. In more detail: a TFTP transfer of a file given in +environment variable 'updatefile' from server 'serverip' is attempted during +boot. The update file should be a FIT file, and can contain one or more +updates. Each update in the update file has an address in NOR Flash where it +should be placed, updates are also protected with a SHA-1 checksum. If the +TFTP transfer is successful, the hash of each update is verified, and if the +verification is positive, the update is stored in Flash. + +The auto-update feature is enabled by the CONFIG_UPDATE_TFTP macro: + +#define CONFIG_UPDATE_TFTP 1 + + +Note that when enabling auto-update, Flash support must be turned on. Also, +one must enable FIT and LIBFDT support: + +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 + +The auto-update feature uses the following configuration knobs: + +- CONFIG_UPDATE_LOAD_ADDR + + Normally, TFTP transfer of the update file is done to the address specified + in environment variable 'loadaddr'. If this variable is not present, the + transfer is made to the address given in CONFIG_UPDATE_LOAD_ADDR (0x100000 + by default). + +- CONFIG_UPDATE_TFTP_CNT_MAX + CONFIG_UPDATE_TFTP_MSEC_MAX + + These knobs control the timeouts during initial connection to the TFTP + server. Since a transfer is attempted during each boot, it is undesirable to + have a long delay when a TFTP server is not present. + CONFIG_UPDATE_TFTP_MSEC_MAX specifies the number of seconds to wait for the + server to respond to initial connection, and CONFIG_UPDATE_TFTP_CNT_MAX + gives the number of such connection retries. CONFIG_UPDATE_TFTP_CNT_MAX must + be non-negative and is 0 by default, CONFIG_UPDATE_TFTP_MSEC_MAX must be + positive and is 1 by default. + +Since the update file is in FIT format, it is created from an *.its file using +the mkimage tool. dtc tool with support for binary includes, e.g. in version +1.2.0 or later, must also be available on the system where the update file is +to be prepared. Refer to the doc/uImage.FIT/ directory for more details on FIT +images. + + +Example .its files +------------------ + +- doc/uImage.FIT/update_uboot.its + + A simple example that can be used to create an update file for automatically + replacing U-Boot image on a system. + + Assuming that an U-Boot image u-boot.bin is present in the current working + directory, and that the address given in the 'load' property in the + 'update_uboot.its' file is where the U-Boot is stored in Flash, the + following command will create the actual update file 'update_uboot.itb': + + mkimage -f update_uboot.its update_uboot.itb + + Place 'update_uboot.itb' on a TFTP server, for example as + '/tftpboot/update_uboot.itb', and set the 'updatefile' variable + appropriately, for example in the U-Boot prompt: + + setenv updatefile /tftpboot/update_uboot.itb + saveenv + + Now, when the system boots up and the update TFTP server specified in the + 'serverip' environment variable is accessible, the new U-Boot image will be + automatically stored in Flash. + + NOTE: do make sure that the 'u-boot.bin' image used to create the update + file is a good, working image. Also make sure that the address in Flash + where the update will be placed is correct. Making mistake here and + attempting the auto-update can render the system unusable. + +- doc/uImage.FIT/update3.its + + An example containing three updates. It can be used to update Linux kernel, + ramdisk and FDT blob stored in Flash. The procedure for preparing the update + file is similar to the example above. diff --git a/doc/uImage.FIT/command_syntax_extensions.txt b/doc/uImage.FIT/command_syntax_extensions.txt index 6185cd8..002818c 100644 --- a/doc/uImage.FIT/command_syntax_extensions.txt +++ b/doc/uImage.FIT/command_syntax_extensions.txt @@ -160,7 +160,7 @@ Note on current image address When bootm is called without arguments, the image at current image address is booted. The current image address is the address set most recently by a load -command, etc, and is by default equal to CFG_LOAD_ADDR. For example, consider +command, etc, and is by default equal to CONFIG_SYS_LOAD_ADDR. For example, consider the following commands: tftp 200000 /tftpboot/kernel diff --git a/doc/uImage.FIT/update3.its b/doc/uImage.FIT/update3.its new file mode 100644 index 0000000..285cf73 --- /dev/null +++ b/doc/uImage.FIT/update3.its @@ -0,0 +1,41 @@ +/* + * Example Automatic software update file. + */ +/ { + description = "Automatic software updates: kernel, ramdisk, FDT"; + #address-cells = <1>; + + images { + update@1 { + description = "Linux kernel binary"; + data = /incbin/("./vmlinux.bin.gz"); + compression = "none"; + type = "firmware"; + load = <FF700000>; + hash@1 { + algo = "sha1"; + }; + }; + update@2 { + description = "Ramdisk image"; + data = /incbin/("./ramdisk_image.gz"); + compression = "none"; + type = "firmware"; + load = <FF8E0000>; + hash@1 { + algo = "sha1"; + }; + }; + + update@3 { + description = "FDT blob"; + data = /incbin/("./blob.fdt"); + compression = "none"; + type = "firmware"; + load = <FFAC0000>; + hash@1 { + algo = "sha1"; + }; + }; + }; +}; diff --git a/doc/uImage.FIT/update_uboot.its b/doc/uImage.FIT/update_uboot.its new file mode 100644 index 0000000..e0d27ea --- /dev/null +++ b/doc/uImage.FIT/update_uboot.its @@ -0,0 +1,21 @@ +/* + * Automatic software update for U-Boot + * Make sure the flashing addresses ('load' prop) is correct for your board! + */ +/ { + description = "Automatic U-Boot update"; + #address-cells = <1>; + + images { + update@1 { + description = "U-Boot binary"; + data = /incbin/("./u-boot.bin"); + compression = "none"; + type = "firmware"; + load = <FFFC0000>; + hash@1 { + algo = "sha1"; + }; + }; + }; +}; |