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author | Benoît Thébaudeau <benoit.thebaudeau@advansee.com> | 2013-04-23 10:17:44 +0000 |
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committer | Ye.Li <B37916@freescale.com> | 2014-01-06 14:04:47 +0800 |
commit | a3b69ac6fafef840bc58003327a3e6343af3e5b9 (patch) | |
tree | 0dc0b656e7d921cadc7805e10dfc6b0ac31d235e /doc | |
parent | 52c6163df27c6d4c8fafed55480c816101be571c (diff) | |
download | u-boot-imx-a3b69ac6fafef840bc58003327a3e6343af3e5b9.zip u-boot-imx-a3b69ac6fafef840bc58003327a3e6343af3e5b9.tar.gz u-boot-imx-a3b69ac6fafef840bc58003327a3e6343af3e5b9.tar.bz2 |
Add mxc_ocotp driver
Add an mxc_ocotp driver for i.MX6.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
(cherry picked from commit 112fd2ec6c1a96c6ff51490c28eb971795a2dd95)
Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'doc')
-rw-r--r-- | doc/README.mxc_ocotp | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/doc/README.mxc_ocotp b/doc/README.mxc_ocotp new file mode 100644 index 0000000..9a53311 --- /dev/null +++ b/doc/README.mxc_ocotp @@ -0,0 +1,50 @@ +Driver implementing the fuse API for Freescale's On-Chip OTP Controller (OCOTP) +on MXC + +This IP can be found on the following SoCs: + - i.MX6. + +Note that this IP is different from albeit similar to the IPs of the same name +that can be found on the following SoCs: + - i.MX23, + - i.MX28, + - i.MX50. + +The section numbers in this file refer to the i.MX6 Reference Manual. + +A fuse word contains 32 fuse bit slots, as explained in 46.2.1. + +A bank contains 8 fuse word slots, as explained in 46.2.1 and shown by the +memory map in 46.4. + +Some fuse bit or word slots may not have the corresponding fuses actually +implemented in the fusebox. + +See the README files of the SoCs using this driver in order to know the +conventions used by U-Boot to store some specific data in the fuses, e.g. MAC +addresses. + +Fuse operations: + + Read + Read operations are implemented as read accesses to the shadow registers, + using "Bankx Wordy" from the memory map in 46.4. This is explained in + detail by the first two paragraphs in 46.2.1.2. + + Sense + Sense operations are implemented as the direct fusebox read explained by + the steps in 46.2.1.2. + + Program + Program operations are implemented as explained by the steps in 46.2.1.3. + Following this operation, the shadow registers are not reloaded by the + hardware. + + Override + Override operations are implemented as write accesses to the shadow + registers, as explained by the first paragraph in 46.2.1.3. + +Configuration: + + CONFIG_MXC_OCOTP + Define this to enable the mxc_ocotp driver. |