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authorSimon Glass <sjg@chromium.org>2015-01-05 20:05:25 -0700
committerSimon Glass <sjg@chromium.org>2015-01-29 17:09:50 -0700
commit5cfc662c496a0e52301a9379f91755b1f8fbf368 (patch)
tree57e898dadd4f05fdbd3c8fc07683a05cf5a7b6e5 /doc/device-tree-bindings/gpio
parent35ea1bfde30a541188ffd24cdf9b3ba79b0e4684 (diff)
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dm: tegra: Bring in GPIO device tree binding
At present the tegra GPIO driver does not fully support the existing device tree binding, but add the binding file to cover the existing partial support. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'doc/device-tree-bindings/gpio')
-rw-r--r--doc/device-tree-bindings/gpio/nvidia,tegra20-gpio.txt40
1 files changed, 40 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/gpio/nvidia,tegra20-gpio.txt b/doc/device-tree-bindings/gpio/nvidia,tegra20-gpio.txt
new file mode 100644
index 0000000..023c952
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/nvidia,tegra20-gpio.txt
@@ -0,0 +1,40 @@
+NVIDIA Tegra GPIO controller
+
+Required properties:
+- compatible : "nvidia,tegra<chip>-gpio"
+- reg : Physical base address and length of the controller's registers.
+- interrupts : The interrupt outputs from the controller. For Tegra20,
+ there should be 7 interrupts specified, and for Tegra30, there should
+ be 8 interrupts specified.
+- #gpio-cells : Should be two. The first cell is the pin number and the
+ second cell is used to specify optional parameters:
+ - bit 0 specifies polarity (0 for normal, 1 for inverted)
+- gpio-controller : Marks the device node as a GPIO controller.
+- #interrupt-cells : Should be 2.
+ The first cell is the GPIO number.
+ The second cell is used to specify flags:
+ bits[3:0] trigger type and level flags:
+ 1 = low-to-high edge triggered.
+ 2 = high-to-low edge triggered.
+ 4 = active high level-sensitive.
+ 8 = active low level-sensitive.
+ Valid combinations are 1, 2, 3, 4, 8.
+- interrupt-controller : Marks the device node as an interrupt controller.
+
+Example:
+
+gpio: gpio@6000d000 {
+ compatible = "nvidia,tegra20-gpio";
+ reg = < 0x6000d000 0x1000 >;
+ interrupts = < 0 32 0x04
+ 0 33 0x04
+ 0 34 0x04
+ 0 35 0x04
+ 0 55 0x04
+ 0 87 0x04
+ 0 89 0x04 >;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+};