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| author | Stephen George <stephen.george@freescale.com> | 2013-03-25 07:40:12 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-05-24 16:54:12 -0500 |
| commit | 49e946cb6ae0448492147ffcb9dcd7d0af1eab4d (patch) | |
| tree | 07118135410c7b399c8ac780b6fa803ceebdfaea /doc/README.t4240qds | |
| parent | 94025b1cd8d9959ebf987a7f6382d513c606ecf1 (diff) | |
| download | u-boot-imx-49e946cb6ae0448492147ffcb9dcd7d0af1eab4d.zip u-boot-imx-49e946cb6ae0448492147ffcb9dcd7d0af1eab4d.tar.gz u-boot-imx-49e946cb6ae0448492147ffcb9dcd7d0af1eab4d.tar.bz2 | |
board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M
Debug trace buffers are memory mapped in DCSR space beyond 4M.
Signed-off-by: Stephen George <stephen.george@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'doc/README.t4240qds')
| -rw-r--r-- | doc/README.t4240qds | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/doc/README.t4240qds b/doc/README.t4240qds index 19e8a8a..a9841fb 100644 --- a/doc/README.t4240qds +++ b/doc/README.t4240qds @@ -86,7 +86,7 @@ The addresses in brackets are physical addresses. 0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mapped under with TLB) 0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory -0x0_f000_0000 (0xf_0000_0000) - 0x0_f03f_ffff 4MB DCSR +0x0_f000_0000 (0xf_0000_0000) - 0x0_f1ff_ffff 32MB DCSR (includes trace buffers) 0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff 32MB BMan 0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff 32MB QMan 0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO |