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author | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2007-09-23 01:29:43 +0900 |
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committer | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2007-09-23 01:29:43 +0900 |
commit | b8685affe614ccf5f4ec66252b30e2e524d18948 (patch) | |
tree | 05bc55b8a4a0451e6500f1f52651d81c0f48f012 /doc/README.ppc440 | |
parent | 69df3c4da0c93017cceb25a366e794570bd0ed98 (diff) | |
parent | 66dcad3a9a53e0766d90e0084123bd8529522fb0 (diff) | |
download | u-boot-imx-b8685affe614ccf5f4ec66252b30e2e524d18948.zip u-boot-imx-b8685affe614ccf5f4ec66252b30e2e524d18948.tar.gz u-boot-imx-b8685affe614ccf5f4ec66252b30e2e524d18948.tar.bz2 |
Merge git://www.denx.de/git/u-boot
Conflicts:
CREDITS
Diffstat (limited to 'doc/README.ppc440')
-rw-r--r-- | doc/README.ppc440 | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/doc/README.ppc440 b/doc/README.ppc440 index 08f34f5..2e04aba 100644 --- a/doc/README.ppc440 +++ b/doc/README.ppc440 @@ -146,12 +146,13 @@ that maps in a single PCI I/O space and PCI memory space. The I/O space begins at PCI I/O address 0 and the PCI memory space is 256 MB starting at PCI address CFG_PCI_TARGBASE. After the pci_controller structure is initialized, the cpu-specific code will -call the routine pci_pre_init() if the CFG_PCI_PRE_INIT flag is -defined. This routine is implemented by board-specific code & is where -the board can over-ride/extend the default pci_controller structure -settings and do other pre-initialization tasks. If pci_pre_init() -returns a value of zero, PCI initialization is aborted; otherwise the -controller structure is registered and initialization continues. +call the routine pci_pre_init(). This routine is implemented by +board-specific code & is where the board can over-ride/extend the +default pci_controller structure settings and exspecially provide +a routine to map the PCI interrupts and do other pre-initialization +tasks. If pci_pre_init() returns a value of zero, PCI initialization +is aborted; otherwise the controller structure is registered and +initialization continues. The default 440GP PCI target configuration is minimal -- it assumes that the strapping registers are set as necessary. Since the strapping bits |