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| author | Ben Warren <bwarren@qstreams.com> | 2007-08-13 21:26:03 -0400 |
|---|---|---|
| committer | Ben Warren <bwarren@qstreams.com> | 2007-08-13 21:26:03 -0400 |
| commit | d1bc6c8d5f4a9c7ca9fb2292d5c65f846dcc3995 (patch) | |
| tree | dd0722cee4758fe40f6a5cc75986ebb1a395aac2 /doc/README.ppc440 | |
| parent | f539edc076cfe52bff919dd512ba8d7af0e22092 (diff) | |
| parent | 8a92b7c60b40ff79e2cc96e13aeac2a531dde473 (diff) | |
| download | u-boot-imx-d1bc6c8d5f4a9c7ca9fb2292d5c65f846dcc3995.zip u-boot-imx-d1bc6c8d5f4a9c7ca9fb2292d5c65f846dcc3995.tar.gz u-boot-imx-d1bc6c8d5f4a9c7ca9fb2292d5c65f846dcc3995.tar.bz2 | |
Sync'd u-boot-net with mainline
Merge git://www.denx.de/git/u-boot
Conflicts:
drivers/bcm570x.c
drivers/tigon3.c
Diffstat (limited to 'doc/README.ppc440')
| -rw-r--r-- | doc/README.ppc440 | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/doc/README.ppc440 b/doc/README.ppc440 index 08f34f5..2e04aba 100644 --- a/doc/README.ppc440 +++ b/doc/README.ppc440 @@ -146,12 +146,13 @@ that maps in a single PCI I/O space and PCI memory space. The I/O space begins at PCI I/O address 0 and the PCI memory space is 256 MB starting at PCI address CFG_PCI_TARGBASE. After the pci_controller structure is initialized, the cpu-specific code will -call the routine pci_pre_init() if the CFG_PCI_PRE_INIT flag is -defined. This routine is implemented by board-specific code & is where -the board can over-ride/extend the default pci_controller structure -settings and do other pre-initialization tasks. If pci_pre_init() -returns a value of zero, PCI initialization is aborted; otherwise the -controller structure is registered and initialization continues. +call the routine pci_pre_init(). This routine is implemented by +board-specific code & is where the board can over-ride/extend the +default pci_controller structure settings and exspecially provide +a routine to map the PCI interrupts and do other pre-initialization +tasks. If pci_pre_init() returns a value of zero, PCI initialization +is aborted; otherwise the controller structure is registered and +initialization continues. The default 440GP PCI target configuration is minimal -- it assumes that the strapping registers are set as necessary. Since the strapping bits |